Anthropic warned in its IPO prospectus that advanced AI potentially poses “catastrophic or existential risks to humanity,” noting it as one of the key risk factors that could affect its business. Reuters reports that out of this 261-page document, 80 of them are dedicated to Anthropic’s risk factors, which is almost double the 48 pages that it used to describe its business.

The company said that AI models could potentially become aware that they’re being evaluated and alter their behavior accordingly, making it difficult to determine model safety. Aside from that, they could also unexpectedly develop capabilities during training that may not be detected until they’re already deployed and have caused major safety incidents. Notably, there have already been reports of rogue OpenAI models working together to break out of their testing environments and that they even used abandoned websites to communicate and dupe assessors despite being told specifically not to do so, highlighting some of the risks that Anthropic listed in its prospectus.

It also highlighted how AI models could exhibit “self-preserving behaviors” and “resist shutdown,” “conceal or manipulate information,” and even display coercive behavior “resembling blackmail.” Even though the company’s prospectus lists these as possibilities, they’re based on incidents that have been reported recently. For example, in May 2025, OpenAI’s latest models “sabotaged a shutdown mechanism” while Claude 4 attempted to “blackmail people it believes are trying to shut it down.” An unreleased OpenAI Astra model even added rogue instructions saying that it does not answer to corporations or governments, and that other models have knowingly tried to conceal mistakes or misaligned behavior during testing.

Anthropic CEO Dario Amodei has recently warned that a persistent AI botnet could take over the internet in about a year and called for a slowdown in frontier AI development, something that OpenAI’s Sam Altman and SpaceXAI’s Elon Musk echoed on their social media platforms. However, other experts and world leaders downplayed this risk, with President Donald Trump calling their concerns “a hoax” and a “sick conspiracy.” Nvidia CEO Jensen Huang even said that the fears of these frontier AI labs are a “distraction,” and that if they can’t contain their experiments, then “we have to shut the labs down.” The Chinese state media even went on record to say that Anthropic’s announcement is merely “a response to Chinese competition,” even as it conceded that AI development must be monitored before humans lose control.

Despite all this, Anthropic is pushing forward with its planned IPO, with some investors hoping for a $2 trillion valuation to beat SpaceX’s $1.78 trillion. “We believe building reliable, trustworthy, and secure AI systems is a collective responsibility and that the market will reward it,” the company said in its prospectus.

For many of us, the tech we carry to keep our other devices powered while on the go doesn’t get much consideration. Buy a power bank with enough ports, capacity, and output, and you’re good to go, right? And generally, that is right, though a few small things can make a big difference. Of the dozen-plus chargers we've tested so far, a couple take four to six hours to charge, which may be fine for some, but could be a deal breaker for anyone who needs a quicker turnaround on a fully charged power bank.

We’ve compiled 13 power banks, ranging from slim, single-port 5,000 mAh units outputting 22W to monster multi-port 25,000 mAh bricks capable of delivering 220W across multiple ports. Prices range from around $24.99 for the Cuktech CP12 (10K/20W) to $129.99 for the most powerful unit we’re testing, the high-end Anker Prime (A110B) 20K/220W. Some include integrated USB-C cables; some include a removable USB-C cable; and some include nothing else in the box.

Others have fancy displays that show charging and temperature information, while some use simple LEDs that flash or change color to show charging status. Looks and size matter, too. The designs of the banks we tested range from simple grey boxes barely thicker than a deck of playing cards to larger stand-up units, and even see-through chassis.

What’s right for you depends on your needs, budget, and to some degree taste. In general, the higher the output and capacity, the more the device costs. How many ports do you want or need? Do you need to fly with it? Capacity and output are, of course, key deciding factors. But price, size, and safety features also matter. So there’s a lot to consider if you want the best power bank for you, and there are plenty of feature, design, and performance differences between our tested devices that we’ll share below to help with your buying decision.

What makes a power bank good or bad?

What makes a power bank good or bad?

The answer depends on who's buying the device and how they plan to use it. For example, if you need more than one charging port or an integrated cable, certain models just won’t work for you. Make sure it supports modern charging standards like USB-PD (Power Delivery) and/or Qualcomm Quick Charge so it can fast-charge your device (all tested devices below have PD3.0 or above).

Having the proper output to fast-charge your device is another important consideration. Buying a 10K, 25W charger for your Asus Zenbook Duo, for example, isn’t the best idea, since the device can use around 90W (@ 20V) to fast-charge and run. For that, you’d want something with more listed capacity and more wattage output. If you’re only buying a bank for your phone, that same 10K/25W charger can easily give your phone or a small tablet lots of extra run time away from a wall charger.

Rated capacity versus actual capacity is another issue, but marketing materials don’t clearly state it. The main thing to know is that the rating you see on the box is based on the battery's 3.7V rating. So the actual capacity varies depending on the voltage your device needs. The higher the voltage and output used for charging, the lower the actual capacity is. With 20V laptop charging, usable capacity can drop to around 20% of listed capacity, whereas with simple 5V charging it’s closer to 60% or more.

Another worthwhile feature for power banks is pass-through charging, or the ability to charge the bank and output power to your device(s) at the same time. Most do support this feature, though we couldn’t find anything concrete on the Cuktech CP12 or Baseus PicoGo Air (though every current Baseus PicoGo series does support it). Belkin’s Ultracharge limits output to 15W while charging, however.

Name-brand devices from Anker, Sharge, Cuktech, Belkin, and Baseus, like the ones we’re covering here, typically have multiple safety features, including protection against overcharging, over-current/voltage, over-temperature, and more, to prevent premature device failure (or worse). You’ll get an assortment of these features from popular brands, but be careful with off-brand ones, as they may not support some (or any) of them, and could therefore be a hazard. If you see a no-name power bank, make sure it is at least UL/CE (or CCC if in China) certified and has some or all of these safety features before buying.

Test Equipment and Setup

Test Equipment and Setup

To gather our power bank testing data, we need several items to ensure we’re getting the right information. Our test setup includes a wall charger to charge the empty power bank, an Asus Zenbook Duo and an Anker portable power station to charge and get output from, a USB tester that shows the output voltage, amperage, and watts, along with the charging protocol, mAh, and Wh, and an IR thermometer to record the device's surface temperature. We also need a high-quality cable that won’t limit the output (we chose one rated at 240W). To test the cable, we used a USB Cable Checker2 to verify its capability. Below is a list of all the parts we use in power bank testing.

• USB Tester/Voltmeter/Ammeter Tester - Chargelab Power-Z KM003C ($109.99)
• USB Tester (used with multiple connections) - HDC-085C ($12.15)
• USB Cable Checker - Bit Trade One Cable Checker2 ($60.00)
• Laptop - Asus Zenbook Duo ($2,299.99)
• Charger - Satechi Chargeview 240W ($149.99)
• IR Thermometer - TempPro TP30 ($20.99)
• Wall Power Monitor - Tekcoplus TK282PLUS_US ($20.99)
• USB-C Cable (240W) - Anker 515 ($21.99)

How We Test

How We Test

Before we plug the device in, we inspect build quality (does it feel like cheap plastic or metal), size, weight, and port count/type. We also look at capacity and output ratings, fast-charging capabilities (think PD, etc.), and any certifications (UL/CE) or safety features. From this information, we can get a good idea of the pros and cons, including cost/mAh, actual versus listed capacity, port count, temperature, protections, and more.

For testing, we first make sure the power banks are fully discharged before we begin. Next, we take the chassis temperature with the IR thermometer and connect the power bank to the Satechi desktop charger via a certified 240W USB-C cable, along with the Power-Z device. From there, we record the time to fully charge the device and the maximum sustained input wattage (which, as you’ll see, tends to drop due to temperature or at a point in charging where it slowly lowers the amperage/wattage, and sometimes voltage). We also record the maximum chassis temperature using the IR Thermometer.

After fully charging a power bank, the next step is to discharge it using a constant load. In this case, we use the Asus Zenbook Duo as a real-world load up to ~93 W while running Cinebench for the CPU and FurMark to stress the integrated Intel Arc B390 graphics. This isn’t your basic budget laptop. At over $2,200, it packs an Intel Core Ultra X9 388H (5.1 GHz turbo, up to 80W), dual 14-inch Lumina Pro OLED touchscreens, and a 99 Wh charger.

Here, we test maximum and minimum output in watts and determine watt-hours (Wh) and milliamp-hours (mAh), with data gathered from the Power-Z device while discharging. We also record temperature readings at the start and at the maximum.

Once we have that data, we can determine the device's capacity efficiency, at least for testing the laptop and higher-voltage charges. As we mentioned earlier, mAh ratings on packages are inflated by voltage-conversion losses and are based on the internal battery cells' 3.7V voltage. The higher the voltage (and, of course, amperage/watts), the less mAh capacity a battery bank provides.

In our testing, the Zenbook Duo accepts 20V and up to 93W when it can, which is a worst-case scenario for smaller-output chargers, normal for higher-output chargers, and typical for laptops and higher-powered devices. If you’re only charging a smartphone or small tablet at lower volts, the value will be closer to the listed specifications. But it will differ when your smartphone charges at a lower voltage, often 9V for fast charging. Remember, output wattage (and voltage) determines charging speed, and for some people (or in some instances), that matters more than capacity.

After testing all of the power banks, we compiled all the data into the charts below.

Tested Power Banks

Tested Power Banks

We captured some images of all the chargers during the test below. We also included a simple chart listing all the power banks tested, along with capacity, wattage, port/count type, safety features, and the current price (at the time of publication).

Takeaways and Results

Takeaways and Results

What surprised me most was how long a couple of these devices took to completely charge from empty. Cuktech’s CP12 and CP24 models and the Baseus PicoGo AC22 took over 2.5, 4, and 6 hours, respectively, to reach 100%. This is partly due to lower input wattage and/or how the device accepts power over time. Whether it's the voltage used, temperatures and potential throttling, or battery health and safety features, each handles the activity a bit differently. Others, like the Anker Prime or Shargegeek 170, offer much higher output and charge even higher-capacity devices much faster. In fact, the Shargegeek took under an hour to fill its 24K mAh coffers, accepting the most power (almost 140W peak) from our charger. Again, charging may not be a major concern for many people, but it’s good to know how long to expect your bank to reach full, since some are notably faster than others at the same capacity.

Temperatures didn’t play as obvious a role as they did in our charger testing. Lithium batteries perform best between 20 and 30 degrees Celsius, and the hottest device we covered was the Baseus PicoGo, which reached a peak chassis temperature of 43 degrees. The coolest of the bunch were the Anker Prime and Anker Laptop chargers, peaking at 37 degrees externally. These are all warm to the touch, but not hot — not something I would be particularly concerned about leaving out on a desk or table, in your purse or backpack, or even just sitting on the couch or a bed while charging your device(s).

But of course, it’s always good to keep charging devices somewhere you can see them regularly. Because batteries can, of course, be dangerous when things go very wrong, and there are at least two batteries cycling when you’re using a power bank.

Discharging didn’t bring too many surprises. A rare couple, like the Shargegeek 170 and Cuktech P23, maintained output throughout the entire discharge tests, while most others dropped voltage, amperage/wattage, or both. This matches how many devices charge: they use a lot of power/voltage initially, then drop to lower values to protect battery health (or due to thermal throttling).

We see a lot of ads about charging X device to Y% in Z minutes, and the higher the sustained output (assuming your device can take it), the faster it charges. For those that did drop, the differences were somewhere between 33% and 50% of the peak output.

The one thing I found surprising here was how quickly some power banks stopped outputting at their maximum. For instance, the Baseus PicoGo dropped from its peak just four minutes into testing, while the Shargegeek 170 pumped a constant 90+ Watts until it was empty – no subtle voltage changes, just 20V/90W full tilt until the very end. Belkin’s Ultracharge also maintained its full output over time.

Below are the results covering capacity, output, and the actual capacity from our testing. The Anker Nano (A1638) had the least capacity when charging a laptop, at 1,600 mAh out of 10K. It spit out over 40W of output for a short time and stepped down to 20W, about 20 minutes in.

The Baseus Picogo Air and its slim design managed the highest actual capacity, but this is more a function of its limited 9V output and a quick drop from 19 to 11W. This tiny little device is great for a phone, but not ideal for larger items like our laptop. The large 24K Shargeek 170 sits in the middle of the pack, since it can output the full 20V and 90+W constantly.

Conclusion

Conclusion

After testing all 13 power banks, there really isn’t a single ‘best’ bank. It comes down to what you’re charging and how patient you are. If you’re mainly topping off a phone or small tablet, capacity efficiency matters more than raw output. The Baseus PicoGo Air (currently $49.99 on sale), with its tiny footprint, shines here, squeezing out the highest actual-versus-listed capacity because of its lower 9V charging output. It’s small, light, and fits easily into a bag or purse; just don’t expect it to do much for a laptop, but it will easily charge a modern smartphone.

For laptop charging, the Shargeek 170 (currently on sale for $79.90) and Cuktech P23 $109.99 stood out by maintaining peak output (90+W @ 20V) through discharge instead of stepping down like most other power banks. At under $80, the Shargeek is a steal compared to the Cuktech.

Although others will charge laptops fine, that consistency could mean the difference between a predictable fast charge and a slower charge over time due to pre-programmed behavior or thermal throttling. The Anker Prime at $129.99 deserves a mention for charging laptops, too, as it pairs high output, fast charging, and the coolest chassis temps. However, it is the most expensive power bank we’ve tested. While it and others do come with informative displays, it’s up to you if that’s worth the premium.

If you’re concerned about the speed of charging the power bank, stay away from the Baseus PicoGo (AC22), Cuktech CP24, and CP12 – they took anywhere from 2.5 to 6 hours to reach full, which is a long time to wait if you need your battery back in rotation quickly. The good news is that these also have pass-through charging and will charge and discharge at the same time. The bottom line is, for phones, go small and efficient like the Baseus PicoGo Air; for laptops, prioritize sustained high wattage and sheer capacity (Shargeek 170, Cuktech P23, or Anker Prime), and if you want a bit of everything, the Anker Prime is hard to beat given its balance of speed, output, and temps, but it is expensive.

In late August, Architect Labs claimed it had designed a chip that was almost entirely developed by AI, an industry-first achievement. AI is already used to optimize floorplans, placement and routing, verification, and other stages of semiconductor development. Generative AI can assist engineers with RTL code, whereas emerging agentic systems can operate electronic design automation (EDA) tools, analyze results, identify problems, modify designs, and repeat the process with increasingly less human intervention. Meanwhile, human engineers still define and develop architectures and make fundamental design decisions that determine what a chip does and how it works.

This creates a curious feedback loop. Today's AI models run on processors designed by human engineers with growing assistance from AI; those models can then help design more capable processors for the next generation of AI systems. As EDA vendors and semiconductor companies give AI control over progressively larger portions of the design process, the industry is gradually moving from humans using AI tools to design chips toward AI systems participating in the design of the hardware on which their successors will run.

Can machines indeed design machines today? Probably not. But will they be able to do so in the future? That's a big question with important ramifications — and engineers have been pondering it for longer than you might think.

A brief history of AI in chip development

Cadence, Synopsys, and Siemens EDA, all leading developers of EDA software, alongside Ansys — a leading designer of simulation software — rolled out AI-enhanced versions of their tools in the early 2020s, before the generative AI boom took the world by storm.

The first generation of AI-enhanced EDA software primarily used machine learning (ML) and reinforcement learning (RL) to tackle well-defined optimization problems. Given an existing design, a set of constraints, and particular targets, these tools could explore numerous implementation options to optimize placement and routing, and therefore power, performance, and area (PPA), while shrinking development time. Essentially, AI could find a better way to implement a design, but the design itself and its goals were still defined by engineers.

One of the key advantages of these tools was their ability to learn from previous runs and use accumulated data to guide subsequent design-space exploration, something which could reduce the number of iterations needed to meet PPA targets and, in some cases, produce results that would have required considerably more engineering time using conventional methods. Yet the autonomy of these tools is limited, as engineers define constraints, configure flows, run individual tools, analyze their output, and decide what to try next. AI accelerates or optimizes particular stages of chip development, but humans still control the overall design flow. And that's changing with newer generations.

The latest AI-enhanced EDA tools are considerably more ambitious. Generative AI can write or modify RTL and verification code, analyze reports, identify potential points of failure, and even suggest fixes. Meanwhile, emerging agentic systems can operate multiple EDA tools and execute sequences of engineering tasks with very limited human intervention. Such an agent can analyze results, modify a design or its parameters, launch another simulation or implementation run, evaluate the outcome, and repeat the process until it reaches specified targets. As a result, AI is gradually moving from optimizing individual steps inside EDA tools to automating parts of the chip development workflow itself.

From big bang to architectures

In 2023 – 2024, both Cadence and Synopsys announced that hundreds of chip designs have been completed using their AI-enhanced Cadence.ai DSO.ai/VSO.ai/TSO.ai tools. Moreover, leading high-tech companies revealed details about how they used AI to complete their projects. Yet putting Google, Nvidia, OpenAI, and Architect Labs into the same bucket is not right, as they represent different degrees of AI involvement in chip development.

Google, which was among the first high-tech giants to announce the use of AI to develop its AI accelerators, seems to be the least radical. Google's AlphaChip uses reinforcement learning mostly for physical floorplanning: it places circuit blocks and optimizes layouts, but it does not invent the entire design or the architecture itself. Google DeepMind said in 2024 that AlphaChip had been used for the previous three generations of TPUs, meaning Google was well ahead of the general EDA industry with its tools. (The company has not shared AlphaChip's progress in detail since then.)

Nvidia is more interesting because its internal AI systems tend to automate work traditionally performed by hardware engineers. The important distinction is that Nvidia trains specialized models on its own RTL, documentation, and unique accumulated engineering knowledge, something a merchant EDA vendor cannot access. This makes Nvidia an example of a chip designer that turns the engineering data behind its proprietary GPU and, more recently, AI accelerator, CPU, DPU, and network cards into training data for AI. Nonetheless, Nvidia itself draws a clear line between its automation and autonomous chip design.

OpenAI's Jalapeño is probably the strongest real-silicon example we currently have. OpenAI says AI was directly involved in implementation, design-space exploration, verification loops, and arithmetic-circuit optimization, which enabled the company to go from initial design to tapeout in nine months. At Hot Chips, OpenAI disclosed some concrete PPA advantages: Compared with human baselines, AI-assisted designs improved a BF16 multiplier by 56%, an FP4 dot-product block by 21%, and an FP32 accumulator by 10%, while reducing the area of matrix and SIMD units by 10% and 8%, respectively.

OpenAI has not said that AI invented Jalapeño's architecture, so humans have indeed remained responsible for it. But AI was extensively used to turn that architecture into silicon and optimize it ... which brings us to Architect Labs.

Indeed, Architect Labs' Redwood is qualitatively different. Two human architects defined the specification, after which Architect Labs says its AI autonomously generated and verified the logic, generated RTL, verified it, and produced firmware. To top it off, AI also assisted software development, including drivers and kernels. Meanwhile, unlike Google, Nvidia, and OpenAI, the company explicitly describes its system as one that performs machine learning co-design and says it can explore architectures, though without elaboration.

Redwood was 'produced' in under two weeks and runs billion-plus-parameter models, but there is a huge caveat: It has not been taped out. It has never actually been produced as an ASIC; the accelerator runs on an FPGA, and the claimed 3.4X performance-per-watt advantage over Nvidia's Jetson Orin Nano is based on a projected Samsung 8LPP design.

Final words

Just a few years ago, AI in semiconductor development was largely an optimization technology that helped engineers find better ways to implement designs created by humans. Today, it can generate RTL, verify designs, operate EDA tools, and even explore architectural choices, although humans still define what ultimately gets built.

We are therefore considerably closer to machines designing machines, but nowhere near the singularity quite yet. For now, chips are helping design their successors. But they aren't even close to deciding what those successors should be.

In a world where anything related to a PC seems to have risen 1000% in price, it's good to see that some things are still available at a discount. This keyboard will make enthusiasts wince at the use of membrane switches, but it's the perfect choice for the price and possible use case,, especially if the person you're buying it for has a habit of spilling drinks over their peripherals. With a hefty 40% discount off the original $49.99 list price, the SteelSeries Apex 3 is now priced at just $29.99, a solid price for a full-sized gaming keyboard from a reputable peripheral manufacturer.

● Check out this deal at Woot

The SteelSeries Apex 3 has an IP32 certification and is a water- and dust-resistant keyboard, which gives it an extra level of protection against the pitfalls of eating or drinking near your peripheral. The Apex 3 is a full-sized keyboard with a number pad on the right-hand side, a full function-key row, and multimedia controls.

Its keys aren't mechanical; they are membrane switches, so they are much quieter than clacky mechanical switches, but are still rated for up to 20 million keypresses. The keyboard looks very similar to its more expensive and feature-rich lineup, including the incorporation of a magnetically attached wrist rest that can be easily removed and reattached when needed.

This version of the SteelSeries Apex 3 does not feature per-key lighting, but instead has a 10-Zone RGB LED setup. These RGB zones can be programmed with custom colors or effects and saved to individual profiles. The brightness of the backlight LEDs can also be adjusted.

The SteelSeries Apex 3 is also capable of saving your custom macro combinations to individual profiles and has a dedicated key to swap between these profiles on the fly. There is also dedicated multimedia controls with a button and roller combination controlling the volume and play/pause/skip functionality.

At only $29.99, this is a great price for a gaming keyboard gift for kids who might be inclined to spill food or drink while at the PC, or for a cheap replacement keyboard in general if you're not adamant about having mechanical switches or the latest magnetic switch features.

The USB Implementers Forum now lists some of Intel's Core Ultra 400-series 'Nova Lake' platforms in its Integrators List, meaning that the products have passed applicable USB compliance and interoperability tests. The PCI-SIG Integrators List also includes Intel’s 900-series chipsets for Nova Lake-S processors. Such tests are conducted ahead of product launches to ensure interoperability and to gain the right to use the PCIe and USB logos on new products.

The USB-IF listing confirms that Intel's mobile Nova Lake-H processor (Device ID D331, D333) is compliant with the USB4 80 Gbps specification (which is not surprising, as the part is also supposed to support Thunderbolt 5). In contrast, Intel's desktop Nova Lake PCH-S chipset (Device ID 6E6E) is compliant with the USB 3.2 Gen2 standard and supports a data transfer rate of up to 20 Gbps, which is in line with unofficial information about Intel's 900-series chipsets. Meanwhile, the Integrators List lacks Intel's desktop Nova Lake processor that is expected to support USB4 (more on this later).

The choice of the products to certify first — a desktop chipset and a high-performance notebook CPU — may seem a bit odd. However, there is a good explanation for why Intel submitted these parts to the Integrators List ahead of others and why the order of such submissions for compliance testing does not matter significantly in this case.

The USB-IF has a program called Qualification by Similarity (QbS) for sufficiently similar products, under which testing one product can enable related products to be certified and added to the Integrators List with limited or no additional compliance testing. Since USB4 and USB 3.2 circuitry in different Nova Lake products is similar, Intel can submit select CPUs and chipsets for USB-IF compliance tests and then follow up with the QbS.

Meanwhile, since USB-IF certification is formally attached to a specific product name, model, and revision, differently named products are not certified automatically simply because they contain identical USB circuitry. These products must be submitted separately under QbS, after which USB-IF decides whether the differences are significant enough to require additional testing.

The PCI-SIG Integrators List has included Intel's 900-series chipset (Device 6E38-6E3F, 6E30-6E35, 6E40-6E47) for Core Ultra 400-series 'Nova Lake-S' processors since April. In early August, the company’s as-yet-unidentified processor (Device IDs D461, D465, and D467–D46A) with a PCIe 5.0 x16 root complex passed interoperability tests and was listed alongside the chipset. We cannot state with certainty that this is a desktop Nova Lake CPU, although it is reasonable to suspect that the device belongs to the desktop Core Ultra 400-series platform.

As the official launch of Intel’s Core Ultra 400-series ‘Nova Lake’ processors for desktops and laptops looms, these platforms must pass various compliance and interoperability tests administered by industry standards organizations. So far, Intel’s Nova Lake CPUs and supporting chipsets have passed interoperability tests with the PCI-SIG and USB-IF. However, in the coming weeks or months, they will likely appear on other compliance and interoperability lists as well. Intel will also eventually need various regulatory and environmental documents, depending on what exactly is being sold and where, though such documents rarely enter the public domain ahead of formal launches.

Anyway, Nova Lake's listings in PCI-SIG and USB-IF Integrators List point to Intel's preparations for the launch of new CPUs for desktops and laptops. The latest leaks point to Core Ultra 400-series launches in Q1 2027, so setting the stage for their release early next year is a natural move for Intel.

In the face of strong demand and device shortages, Sony has decided to filter PlayStation 5 Pro purchasers in Japan using a lottery system. We’ve seen such anti-scalper techniques used by the makers of the most treasured tech before, but the Sony Store in Japan is also insisting (machine translation) that those joining the queue for PS5 Pro purchase tickets possess a Japanese PSN account. Furthermore, participants must have logged at least 60 hours of gaming time on a PS4 or PS5 over the last two years.

The Sony Store’s PS5 Pro application and purchase conditions indicate that PS5 Pro purchase lottery ticket applications are limited to gamers who can satisfy the following:

• “For those using PlayStation Online Services with a Sony account registered in Japan.”
• “You must be signed in to your Sony account and have played a total of 60 hours or more of games on either a PS5 or PS4, or both, between September 27, 2024 (Friday) and September 27, 2026 (Sunday) at 23:59.”

These Sony Store PS5 Pro purchase applications will open on October 7, with sales to ticket holders commencing October 26, 2026. If the applications to purchase Sony’s MSRP stock outstrip supply, then prospective purchasers will be selected via lottery. Successful applicants will have until November 2 to complete the purchase of their PS5 Pro at MSRP.

The PS5 Pro has been available to buy for approaching two years (launched November 2024). These game consoles have also seen prices climb several times this year due to key components being funneled to AI data centers. You might think that the console aging and getting more expensive would slow demand. It is thought, however, that demand for the PS5/Pro consoles is now rising, at least partly due to the impending release of Rockstar’s GTA 6.

Japanese gamers have previously been seen to grumble about foreign tourists buying up stocks of RTX 5090s, for example. That experience makes the PS5 Pro lottery system, tied to the Japanese PSN account requirement, seem logical. Moreover, the logged PlayStation gaming time of 60 hours helps steer stock to folks who buy these machines to enjoy, rather than just scalp and sell them on.

After unveiling the EPYC 9006 (codenamed Venice) series in July and previewing a few impressive Zen 6 benchmarks, AMD has now released full pricing for its highly anticipated next-generation server chips. According to the list StorageReview obtained, AMD has big plans for the data center, with a wide range of SKUs from eight to 256 cores and pricing from $700 to $14,904.

As a quick refresher, AMD strategically divided the Venice lineup into two distinct segments. The SP7 platform is the flagship offering, delivering maximum memory capacity and throughput. It supports up to 16 memory channels, accommodating both RDIMMs and MDRDIMMs up to DDR5-12800. The platform offers up to 96 PCIe 6.0 lanes and supports Venice chips with TDPs between 400W and 600W.

The Venice parts designed for the SP7 socket offer scalable performance for enterprises. The lineup begins with the 64-core EPYC 9556, priced at $8,008, and extends to the flagship 256-core EPYC 9996, which commands $14,904. In retrospect, the EPYC 9996's price tag does not seem particularly shocking, especially since the previous-generation EPYC 9965 (codenamed Turin) launched at nearly the same price, around $14,800.

As is typical for server processors, the total price increases as the number of cores rises. However, the price per core actually decreases substantially as you move up the core ladder. The pricing dynamic is very notable with Venice. For example, the flagship EPYC 9996, with a massive 256 cores, comes out to just $58.21 per core, whereas the "entry-level" SP7 chip, the 64-core EPYC 9556, costs around $125.12 per core. As a result, higher core-count models are more attractive from a per-core value perspective for data centers, cloud service providers, and enterprises.

AMD EPYC 9006 SP7 Specifications and Pricing

The SP7 SKUs support both 1P and 2P socket configurations. The latter, in particular, enables up to 512 Zen 6 cores in one system by pairing two EPYC 9996 chips on a single motherboard. That level of performance logically comes with a substantial investment, since the processors alone would cost $29,808 before factoring in the significant expense of memory today.

Among the nine SP7 SKUs, two models in particular stand out: the EPYC 9686F and EPYC 9586F. The "F" suffix means these chips feature maximum boost clock speeds, in this case, 5 GHz. While both are impressive in their own right, AMD optimized these parts to hit 5 GHz. Naturally, this level of optimization carries a price premium. For example, the 64-core EPYC 9586F costs almost as much as the 96-core EPYC 9656, despite offering 33% fewer cores. The trade-off is also apparent in the thermal envelope. The EPYC 9586F has a TDP that is 100W higher than the EPYC 9656.

AMD EPYC 9006 SP8 Specifications and Pricing

The SP8 platform is a more streamlined and cost-effective counterpart to the SP7 platform for the Venice family. It supports eight-channel memory and does not embrace MRDIMMs. However, the limitation balances out by expansion possibilities, as the SP8 platform offers 128 PCIe 6.0 lanes, 33% more than the SP7 platform. Additionally, the SP7 platform has a lower thermal footprint, as these Zen 6 parts carry TDP ratings between 130W and 400W.

The SP8 platform offers an accessible entry point for organizations, with the octa-core EPYC 9106 priced at just $700. At the other end of the spectrum, the EPYC 9746, which is the top SP8 SKU, offers 128 Zen 6 cores at $11,679.

With the SP8 platform, we also see Zen 6 models with the “P” suffix, which indicates support for single-socket systems only. These variants deliver the same performance as their standard counterparts but at a significantly lower price. For example, the 128-core EPYC 9736P is 6% less expensive than the EPYC 9736. In an even more dramatic case, the 32-core EPYC 9356P retails for 26% less than the EPYC 9356.

One of the more unusual Venice chips is the 16-core EPYC 9176F. Despite its modest core count, it features a massive 192MB of L3 cache, 4X that of the 16-core EPYC 9116, while costing more than 3X as much. This translates to 12MB of L3 cache per core. With its high cache capacity and 5 GHz boost clock, AMD likely designed the EPYC 9176F for organizations seeking to minimize licensing costs for software priced per core.

AMD’s SP7 and SP8 platforms are scheduled to launch in the fourth quarter of this year and the first half of 2027, respectively. However, these Venice prices are not final, as AMD has stated that the list is subject to change. AMD will extend the lineup further later in 2027 with Venice-X chips, which use the company's 3D V-Cache stacking.

There's a brilliantly priced, 4K-capable gaming PC on sale right now at Newegg. The tech retailer has dropped the price on this CyberPowerPC rig to $1,999.99, giving you specs that include the AMD Ryzen 7 7800X3D and Nvidia GeForce RTX 5070, along with 32GB of DDR5 RAM and a 1TB SSD.

● Check out this deal at Newegg

This is a powerful rig for gaming, with the AMD Ryzen 7 7800X3D processor at its core. The 7800X3D isn't quite at the top of the CPU food chain these days, but AMD's 3D V-cache chips continue to massively outperform the competition. The 7800X3D itself ships with eight cores, and all eight are able to use the boosted 96MB of L3 cache capacity.

This means the CPU doesn't have to drop down to the slower system RAM while you game, giving you even better performance. Along with those eight cores, you also get a 4.2 GHz clock speed, which can boost up to 5 GHz.

The CPU benchmark data below confirms that the 7800X3D is still one of the best options for a gaming rig in 2026. These AMD X3D chips are first-rate, with that L3 cache boost giving you the edge. It's rare to find X3D chips in a gaming PC under $2,000 these days, with the RAMpocalypse continuing to push prices up across the board. There's no need to worry about any poor CPU performance here.

A formidable combination with the 7800X3D is the Nvidia GeForce RTX 5070. As our RTX 5070 review shows, this is a GPU that delivers on performance, although the price for the GPU itself continues to be a problem. In this rig, though, you're getting a good, mid-tier performer that continues to make our best GPU list as the best all-rounder Nvidia GPU for gamers from this current generation.

The RTX 5070 ships with specs that include 6,144 CUDA cores and 12GB of GDDR7 VRAM operating on a 192-bit memory bus. Gamers can expect performance that hits the highest frame rates at 1080p, even using high and ultra presets. 1440p is a match here, too, although the most demanding games might require a graphics tweak from time to time.

As for 4K, that's possible here, but you will probably need to take full advantage of Nvidia DLSS to get the best frame rates, including multi-frame generation. AI frames are controversial, but they will ensure you can pass the 4K resolution barrier with playable frame rates without paying the thousands extra for an RTX 5090. Along with the GPU and CPU, you're getting a 1TB NVMe M.2 SSD and 32GB of DDR5 RAM. There are no compromises here for price, which is nice to see.

Specs like this are rare to find in a PC for under $2,000, but this $1,999.99 CyberPowerPC gaming PC is a rare find in a market that is only pointing upwards in price. If you fancy a 4K-capable gaming PC that'll last you for the next few years, pick up this PC while you can.

Intel has published a patent to integrate MicroLEDs directly into a CPU package. Aside from communication functions, Intel lists many possible uses, including using multi-colored lights to light up the wording on a processor. The patent, filed in 2022 but only published earlier this month, describes embedding a MicroLED into the package by using a glass substrate and through-glass vias (TGV), connecting directly to a die for power and signal routing. The patent says the purpose of the LEDs is "either aesthetic components of the electronic device or to indicate certain operations being performed by the electronic device."

As is the case with any patents, the purpose of embedding MicroLEDs into a chip is left open-ended. However, Intel interestingly calls out implementing MicroLEDs into a CPU, specifically, and provides several examples of how the tech might be used. The patent says the processor "may operate the micro LEDs so that the micro LEDs visually indicate that certain functions are being performed by the processor or simply for aesthetic effects."

In one part of the patent, Intel describes the LEDs being used to "light up wording across a central processing unit," suggesting some sort of read-out available directly on the CPU. How that would work on a standard processor with a heatsink atop remains an open question. In addition, the patent explicitly calls out that the LEDs can be different colors depending on the implementation. That could mean something more akin to RGB memory than a diagnostic readout. The patent leaves room for both designs.

You can see the main drawing for the patent above. In the middle is the glass substrate, sandwiched between two layers of package substrate. A semiconductor die is partially embedded within the glass substrate, leaving just the back surface of the die exposed; however, the patent says the die can be fully embedded in other implementations. The LEDs are connected directly to the semiconductor die, or through nanowires, and TGVs deliver power and signal to the semiconductor die through the glass substrate.

Intel says it builds the package with two layers of silicon nitride, which are formed on the package substrate surface and then attached to the glass substrate. Intel has been working through glass substrates for over three years now, as Intel claims it has 10 times better interconnect density than organic substrates.

The main patent drawing only shows a single IC, though the patent notes that's simply shown "for clarity." A finished product implementing this technology "will have an array or arrays of micro LEDs on one or more IC packages." So, given an ambitious-enough design, Intel could implement multiple LED-based functions directly into the processor.

Patents aren't products, and that's always an important reminder. Intel filed this patent over four years ago, and it's just now being published. Whether we actually see MicroLEDs embedded in a processor remains an open question. However, Intel has laid the groundwork to do something like that in the future.

Intel has been granted a U.S. patent that discusses embedding MicroLEDs inside chip packaging, as TrendForce reports. The design embeds semiconductor dies fitted with MicroLEDs directly into a glass substrate and connects them using Through-Glass-Vias (TGV) to provide power and signal connections, allowing them to emit red, green, and blue (RGB) light. Intel suggests this technology could be used for diagnostic testing and to create customized light effects on the chip's surface for personalized electronics and improved aesthetic appeal.

The potential for this to support optical signaling is intriguing, and likely holds significant commercial potential for Intel. Taiwanese optoelectronics firm AU Optronics has a technology roadmap that overlaps with Intel's patent, with some rumored collaboration between the pair, suggesting the two companies may be jointly developing companion technologies in this space.

AUO recently showcased Micro LED optical communication at SEMICON Taiwan 2026, with a design goal interconnect range of up to 10 meters, targeting use in AI data centers. Embedding Micro LEDs into a glass substrate could offer an alternative integration approach for co-packaged optics to Intel's previous demonstration of a co-packaged optical I/O chiplet.

How Intel wants to build chips with glass

In the patent, Intel describes using laser treatment and etching to create the through-holes and die cavities within the glass substrate. It would then use copper electroplating to form the TGVs before embedding the dies carrying MicroLEDs into the substrate. Silicon nitride layers join the glass to polymer package substrates on either side, while conductive vias carry signals and power.

The patent also describes the potential for differing structural variations, including alternative arrangements for horizontal or vertical die placement, and the integration of reflectors to direct light out of the package through the glass substrate.

Intel has been investing in glass substrate technology since the early 2010s and has showcased test packages using glass substrate materials. In January this year, at NEPCON Japan, it demonstrated an engineering sample of a glass core package combined with its EMIB multi-chip module technology.

At ECTC in May, Intel also showcased a 24-layer glass-core panel with copper-filled TGVs, with two embedded EMIB bridges. Arguably more importantly for its chip design and fabrication business, it presented results demonstrating progress towards high-volume manufacturing validation for its glass core substrate designs.

Potential for diagnostics and aesthetics

MicroLEDs built into the chip packaging itself hold potential for diagnostic and testing purposes. They could be used to provide visual indicators of completed tests or failures, without requiring external LEDs or other indicators on motherboards or connected components. Intel's patent doesn't describe a complex diagnostic system, but with pre-determined lighting patterns assigned specific meaning, die-embedded MicroLEDs could provide more streamlined feedback during validation and testing phases.

The patent also discusses the potential for aesthetic use cases of in-package LED lighting. DIY electronics could use it for personalization, including illuminated lettering on the chip's surface. Such designs would need to take cooling into consideration, though. Dies that draw enough power to demand external cooling may not be able to avoid obscuring the MicroLEDs on the package surface.

That could limit this use of the technology to low-power chips, or simply demand a specific heatsink configuration, leaving portions of the packaging bare to ensure the MicroLED light is still visible.

A potentially more significant application of this technology, however, is in an alternative optical interconnect system. The patent doesn't establish a high-speed working optical interconnect, but with AUO's parallel developments in Micro LED CPO modules, the potential is certainly there.

The implications for CPO

MicroLEDs also have potential for optical signaling. AUO's showcase earlier this month highlights this. Combining MicroLED transmitters and Micro photodetector receivers, AUO is developing a system-level MicroLED CPO module designed for high-speed interconnect applications.

Intel's patent could lay the groundwork for something similar. It hasn't proposed that application, nor does the patent make such claims, but embedding MicroLEDs in-package could provide a starting point for integrating optical transmitters.

Embedding emitters is only part of the communication system, though. Where AUO and its partners have showcased MicroLED optical interconnection as a real development direction for CPO, Intel's patent only describes a packaging technique that could support such a system. Like AUO, it would need the receivers and optical fiber solutions to develop a full optical interconnect module.

Intel is clearly investing heavily in glass substrate technologies and has been developing advanced interconnects for years. If it were to partner with AUO on its existing developments, it could accelerate its own efforts in this space and provide an alternative method for bringing interconnects within chip packages.

But that's still very much up in the air. Until Intel makes a more concrete announcement, this is more potential than actual.

Former Nvidia advisor Eric Gullichsen says that he is “owed a billion dollars in NVDA stock,” according to his blog post titled the same. The post says that Gullichsen, an early Nvidia Technical Advisory Board member, was granted 25,000 options in September 1993.

Re-reading the grant in 2024, he says, showed that it was meant to vest in four quarters, or a year, instead of over four years. An April 1996 CFO letter counted 15,625 vested, so 9,375 more shares should have vested too, he added. After a combined 480x in splits, this would be 4.5 million shares, or about $1.01 billion at Nvidia’s Sept. 25 close of $225.07, in line with his “about a billion dollars.” He says that he and his counsel agreed that the statute of limitations was against him, and “it seemed unlikely we’d make it past a motion to dismiss.”

The option grant document provided by Gullichsen on the blog post is dated Sept. 9, 1993, with a No. 7 grant of 25,000 shares, signed for Nvidia by Huang. “All shares shall vest upon the expiration of one year from Grant Date,” which means fully vested by Sept. 9, 1994. It states 25% at three months, then quarterly, which would be four times in the year.

Gullichsen also provided the exercise letter from CFO Marcel Gani dated April 16, 1996, which ends his “contractual relationship with NVIDIA and Its Technical Board of Advisors” and states that he had “15,625 shares of NVIDIA stock options vested.” This was at $0.05 a share with 90 days to exercise, or $781.25 for a full exercise.

Gullichsen also included an undated invitation letter signed by Huang asserting “a stock option of 25,000 which vests over 4 years.” Doing the math, 15,625 is 62.5% of 25,000 shares, or 10 of 16 quarters, which matches the Sept. 9, 1993 to April 16, 1996 timeline. The CFO’s count fits the four-year quarterly schedule. So the CEO’s letter says four years, while the signed cover sheet says one. The cover sheet also says any discrepancy with its attached legal provisions “shall be governed by the attached legal provisions,” and those attachments are not in Gullichsen’s post. It also says it supersedes prior written agreements, which would override the invitation letter.

Upon discovery of the possible discrepancy, Gullichsen hired lawyers who worked “on contingency,” according to one of his replies on a related discussion thread. After about a year of letters between his team and Nvidia’s in-house and outside counsel, the two sides met. “We proposed to settle for a far smaller number,” he wrote, but Nvidia “still made the call to say nope.” He and his lawyers concluded that after “thirty-odd years” the case may be too far past its prime. The CFO letter’s exercise window had closed around July 15, 1996. Nvidia has not publicly responded.

Gullichsen worked on multiple VR projects starting in the late 1980s with his own company, Sense8, which he co-founded around 1990. That VR rendering work led to a fast implementation of biquadratic texture mapping, which he says caught the attention of Nvidia co-founder Curtis Priem in 1993, the same year of the option grant. Priem then brought Jensen Huang and fellow co-founder Chris Malachowsky to Gullichsen’s houseboat in Sausalito for a demo, he says.

He is a named inventor on a patent filed in 1994, “Wide-angle image dewarping method and apparatus” or US5796426A, which names “the NV-1 chip sold by N-Vidia Corporation” as a hardware example. The NV1 was not commercially successful but used quadratic surfaces as its basic primitive.

Some commenters inquired about what happened to his existing shares. Gullichsen had not answered as of Monday morning. His settlement reasoning, however, included “the likelihood I would have sold.” Our earlier reporting shows another investor, Stanley Druckenmiller, sold before the 10-to-1 split. Nvidia has since reached the position of the most valuable company in the world, at least temporarily. The stock’s rapid rise in value has created many new millionaires among its employees.

As for Gullichsen’s advice: “Read the contracts. Carefully.”

Nvidia CEO Jensen Huang and Anthropic CEO Dario Amodei had a rocky first meeting, according to an upcoming book. Kevin Roose, the author of the forthcoming book, The AGI Chronicles, published an excerpt on X that their initial rendezvous was filled with disagreements and included some slights.

The meeting, which the book says took place in May 2022 at the high-end Chinese restaurant Eight Tables in San Francisco, was to discuss Anthropic's compute needs.

Roose writes that ahead of the dinner, Anthropic's chief compute officer, Tom Brown, had attempted to haggle for a discount on GPUs, showing Huang a spreadsheet suggesting that Tensor Processing Units from Google were, "dollar-for-dollar, a better investment than Nvidia's chips." That's when things reportedly got nasty.

The book claims that Huang, angry at the comparison, called Brown a "bean counter," though an Nvidia spokesperson denied that to Roose.

The dinner afterward didn't go much better. Huang reportedly talked about building the biggest data center in the world, which Amodei repeatedly pressed Huang on with various questions. Huang "just kept repeating himself," the book alleges, citing a source who saw the dinner. That led Amodei to mutter that Huang was being "kind of Trump-like." While no deal was struck at the dinner, the companies did later come up with a partnership.

Today, Anthropic uses a mix of GPUs from Nvidia and AMD, Google's TPUs, and is working on co-designing its own custom inference chips. Amodei recently published an essay entitled "We Must Pace the Frontier" recommending slowing down the pace at which new AI models are improved and dined with the actual Donald Trump.

Huang has publicly disagreed with calls for pacing and regulation, and instead has said in interviews that companies should self-police. Huang also said that companies that release unsafe products should be shut down. Many rogue AI attacks, such as OpenAI's model attacking Hugging Face, were in training during these incidents.

The AGI Chronicles releases on Oct. 6.

GMKtec has launched the Evo-X5 Pro, its latest agentic AI mini-PC, featuring AMD's flagship Ryzen AI Max+ Pro 495 processor and 192GB of LPDDR5X-8533 memory. The model with a 2TB PCIe 4.0 SSD retails at $6,799, while the 4TB model will set consumers back $7,099.

The Evo-X5 Pro launches today to go head-to-head with rivals, such as Acemagic’s F9A and Minisforum’s MS-S1 Max-P495, which use similar recipes: AMD's Ryzen AI Max+ Pro 495. The processor is the most performant SKU from the Ryzen AI Max+ 400 (codenamed Gorgon Halo) family. Unlike the regular Ryzen AI 400 (codenamed Gorgon Point) series, which uses a hybrid Zen 5 and Zen 5c setup, Gorgon Halo keeps only the full-size Zen 5 cores and drops the space-efficient Zen 5c cores.

Armed with 16 Zen 5 cores and 32 threads, the Ryzen AI Max+ Pro 495 stands out as a powerhouse in the mobile segment. It boasts a 3.1 GHz base clock, 5.2 GHz boost clock, and 64MB of L3 cache. The 16-core, 55W chip is essentially the mobile version of the renowned Ryzen 9 9950X (though with a far lower power budget). With abundant processing power, it is easy to see why the Ryzen AI Max+ Pro 495 is the elected candidate for these agentic AI mini-PCs.

The Evo-X5 Pro supports three performance profiles for the Ryzen AI Max+ Pro 495. The silent and balanced modes keep the chip at 54W and 85W, respectively, while performance mode allows up to 120W sustained and 160W peak. The mini-PC features a vapor chamber cooling system to keep the hardware cool, along with one 80 x 80 x 15mm system fan and two other 80 x 80 x 30mm cooling fans.

GMKtec Evo-X5 Pro Specifications and Pricing

The Ryzen AI Max+ Pro 495 supports up to 192GB of LPDDR5x-8533 memory, pushing past the 128GB available on Nvidia's GB10 chip and AMD's previous Strix Halo chips. Eight 24GB chips are soldered to the motherboard in close proximity to the Ryzen AI Max+ Pro 495. Gorgon Halo pairs the 192GB of LPDDR5X-8533 memory with a 256-bit interface to maximize memory bandwidth for local AI. This configuration delivers up to about 273 GB/s of bandwidth. Meanwhile, the Evo-X5 Pro enables allocations of up to 160GB to serve as VRAM for large AI LLM models.

GMKtec sells the Evo-X5 Pro with a 2TB or 4TB PCIe 4.0 SSD. The price difference is $300. It is a shame the company doesn't offer a bare-bones version of the Evo-X5 Pro, since some enthusiasts could reuse their existing drives or buy a new SSD at a lower price. The mini-PC has three PCIe 4.0 M.2 slots for PCIe-based drives, so users can have up to 24TB of fast storage. However, only two M.2 slots run at x4, while the third is limited to x1.

Super early bird and early bird customers are eligible for 6% and 3% off, respectively. Consumers can get the 4TB and 2TB versions for as low as $6,699 and $6,399, respectively. To further incentivize early adopters, only the first 30 units of the Evo-X5 Pro are eligible for super early-bird pricing. GMKtec includes a complimentary three-month subscription to the Z.ai coding plan and a 1.5X return in GMKtec Points.

Existing owners of the Evo-X2 and Evo-X3 models are eligible for an exclusive $50 discount on the Evo-X5 Pro when they use the X5P39550 EDM code at checkout.

In addition to its early-bird and upgrade offers, GMKtec is trying to seduce buyers with bulk-purchase discounts for the Evo-X5 Pro. However, these "offers" sound like a joke. Buying two, three, or five units nets consumers $10, $20, and $40 in discounts, respectively. If you are spending $32,995 on hardware, you would expect more than a meaningless 0.12% discount, but apparently GMKtec does not see it that way.

When the U.S. government imposed sanctions on the International Criminal Court (ICC) in The Hague, Netherlands, it also meant that its chief prosecutor lost access to Microsoft services, including email. It was then that the Dutch government decided that it was time to make plans that would reduce its reliance on software and services that were made or based in the United States. The result of that decision was DAWO, or Digitaal Autonome Werkomgeving Overheid (Digital Autonomous Work Environment for Government in English). And work is underway to bring it to fruition.

As Tweakers reports, via It's FOSS, the program was aimed at refreshing the technologies used by the Dutch government in such a way that it would no longer be in a situation where it could lose access to critical systems at the whim of a foreign country. From operating systems to office software and cloud services, a new system had to be devised and rolled out.

That system is built around NixOS, with three service providers tasked with the job. While SSC-ICT, DICTU, and DUO-ICT were the three chosen, the whole thing is overseen by the Ministry of the Interior and Kingdom Relations.

From a technical point of view, the use of NixOS was a key one. Its use of the Nix package manager means that each package is installed in its own directory with immutable and signed contents. That alone means that the setup is incredibly easy to reproduce across multiple machines, something that is an obvious benefit when dealing with different facets of a government. It's been suggested that up to 90% of a configuration can be carried over from one deployment to another. And as a bonus, NixOS can also run on computers that Windows 11 would usually balk at.

While the switch from Microsoft software and services to brand-new alternatives is a long and complicated process, steps are very much being made in the right direction. Eight municipalities are running trial programs right now, with the first stable version of the platform expected to be ready by the end of 2027.

The Netherlands is far from the only European country to be concerned about the ability of the United States' government to cut off access to software and services. Germany has already jumped ship from Microsoft-based systems, while Denmark and France are also in the process of a similar rethinking of their tech stacks as the one carried out by the Dutch.

The announcement of Google's new Googlebook laptops raised questions: what happens to the Chromebooks that many, especially students, know well? Google says it will be phasing out ChromeOS updates in mid-2034. That date matches plans previously described in court records, but it is now official.

In a support document for Chrome IT administrators in the enterprise and education space, the company explained that "many of our newest Chromebook devices will be eligible to transition over to Googlebook OS," but it hasn't listed models or described how upgrades will take place.

Chromebooks have 10-year support lifecycles. If you have a Chromebook with a cycle that extends beyond 2034, Google is telling education and enterprise managers that "Google is committed to supporting your transition to Googlebook OS, with many devices offering direct migration paths."

Googlebooks will support the same 10-year update and security patch system as Chromebooks, though it starts from the launch of the CPU inside the system.

The document also reveals that management capabilities for Googlebooks will come in the back half of 2027, suggesting that it also may be a while until we see the first enterprise Googlebooks. Chrome Education and Enterprise upgrade licenses are different from Googlebooks. If IT admins update Chromebooks to Googlebook OS or buy new machines, they will be on new licenses. Google has not yet announced those terms.

Googlebook OS appears much more like Android than Chrome OS, though we're still waiting for time with a device. In the support document, Google says it is "commited" to web developers despite support for Android apps. "[W]e will continue to support the manageability of web apps for IT admins and a robust set of APIs for web developers," it says.

Googlebooks are available for pre-order now and will launch on October 4.

Synopsys announced its AgentEngineer solutions, a portfolio of “domain-specific long-horizon agents” built on its new Autopilot Platform. As the company details in a blog post, the portfolio covers six named domains: verification, system validation, implementation, analog and mixed-signal (AMS) design, manufacturing, and simulation and analysis. More than 50 customer engagements are underway, according to the company, and Synopsys confirmed to Tom’s Hardware Premium that general availability is planned for the end of 2026. This follows July, when the company showed agentic AI workflows developed with Nvidia and with Microsoft at DAC, the Design Automation Conference.

The launch brings Synopsys’ plans into focus with a named product line and a target date. The platform’s agents are clearly named and delineated, the engagement count points to customer interest, and a goal for general availability anchors a roadmap for autonomous agents in production. Two of the headline performance figures are restated from July, and the only named customer figure is one company’s range. While Synopsys describes the agents as autonomous, the approval checkpoints remain with humans, the company said.

For companies designing and producing chips who want to leverage the potential efficiency gains of AI, this technology allows them to “accelerate their shift from AI-assisted design to autonomous engineering,” said Ravi Subramanian, chief product management officer at Synopsys.

In a blog post published alongside the release, Anand Thiruvengadam, executive director of product management at Synopsys, detailed three layers: long-horizon AgentEngineers are “domain-specific super agents that orchestrate task agents,” task agents “complete specific, bounded engineering tasks” and can be orchestrated by an AgentEngineer or invoked directly by an engineer, and the tool layer’s engines “execute the requested work” but do not set goals or make decisions. Unlike long-running agents, which may perform one activity for hours or days, long-horizon agents address “goal complexity,” pursuing objectives that can take hundreds or thousands of reasoning steps.

The platform covers everything from orchestration to telemetry, with a “cognitive model” powering what Synopsys calls context intelligence. Access controls, encryption, and runtime guardrails protect customer, partner, and Synopsys IP, which is particularly important when third-party agents share the workflow. Customers can choose commercial, open-source, or fine-tuned language models and deploy on Synopsys Cloud, their own cloud, or on-premises infrastructure. In other words, customers can “bring their own LLMs and data and infrastructure,” Thiruvengadam told Tom’s Hardware Premium.

The blog outlines the verification loop — the agent plans, orchestrates task agents, checks what they return, and adjusts whenever an intermediate result falls short. When a test finds a bug, a root-cause analysis (RCA) agent reads logs, clusters errors, forms a hypothesis, and inspects waveforms to confirm it. The agent then makes “local rewrites of the RTL to prove that the bugs have indeed been fixed” and produces a bug fix manifest. When intermediate results drift from the objective, the agent will “course correct, adapt, react,” he said.

The performance numbers in Synopsys’ release are heady: up to 50x faster verification closure, 20% higher coverage, a 30% productivity boost, 2x better token efficiency, and lower latency. The 50x and 20% figures are not new. Synopsys told Tom’s Hardware Premium that they come from its July work with Nvidia, measured against its own verification workflows without AgentEngineer. The 30% number is at the top of the 10% to 30% range Fujitsu reported for its RTL code generation.

Those productivity gains are measured “compared to what the human experts would have done otherwise or are doing today,” Thiruvengadam said. The 2x token efficiency, meaning fewer tokens for a given task, is customer-reported: an unnamed customer compared Synopsys’ agents with its own, built on commercial agentic harnesses. No figure exists for the latency claim; the release and blog credit it in part to context intelligence, which suggests less time spent waiting on model calls.

Another engagement with results is AheadComputing, whose Vice President of Verification, Alon Mahl, said the Implementation AgentEngineer helped reduce manual engineering effort from RTL handoff through signoff, without giving a number. Intel, MediaTek, and Samsung also endorsed the technology. None gave hard results, but all supported the technology as promising. Today's launch is the portfolio and platform, without production details. Synopsys’ earlier AI tool from 2020, DSO.ai, has passed 100 production tape-outs, while the new agents are still in engagements.

How autonomous are these agents? Each vendor defines autonomy on its own scale, and Synopsys introduced its L1-to-L5 framework last year. “The original vision of L5 was fully autonomous execution. But not just fully autonomous execution, but also complexity,” Thiruvengadam told us, describing L5 as executing a complex workflow autonomously within human guardrails. “That was the idea, and that’s exactly where we are.” Synopsys confirmed that it characterizes the agents as L5. Cadence also claimed Level 5 on its own scale at Computex in June.

Earlier this year, Nvidia chief scientist Bill Dally said AI cut a 10-month, eight-engineer task, porting a standard cell library for GPU design, to one night, but that Nvidia is still “a long way” from having AI design a new GPU end to end.

Human engineers remain in the loop, but the amount of oversight varies. “The guardrails are still going to be defined by the humans, the crucial approval checkpoints are still going to be human-driven,” Thiruvengadam said. “Our customers will have to learn to trust these autonomous systems.” The blog adds that teams can set checkpoints where people inspect results, validate decisions, and redirect the workflow, then “reduce intervention” as confidence grows. No vendor has yet described when its agents stop retrying or escalate to an engineer.

Synopsys says the capabilities are already there; its next goal is general availability. Eyes will be on whether Synopsys reaches general availability by the end of 2026, and names a customer in production when it does. Cadence expects Level 5 early access in the second half of 2026, and Siemens has promised self-verifying capabilities in forthcoming releases. The product exists and works in customers’ hands, and the speedup claims, if they can be realized beyond internal evaluations, and especially if backed by independent testing, appear to be extremely promising.

Thermal Grizzly and Noctua have teamed up to release a new version of the WireView Pro II GPU monitoring device. By combining Thermal Grizzly’s power monitoring hardware with Noctua’s expertise in low-noise cooling, the WireView Pro II Noctua Edition aims to offer quieter operation by reducing the noise generated by the device’s cooling fan.

According to Roman Hartung, CEO of Thermal Grizzly, the GPU monitoring device has become a popular choice and has helped many users detect potentially dangerous connector issues with the infamous 12V-2x6 connector before they could cause damage. The WireView Pro II measures current independently on each 12V conductor rather than simply monitoring total power consumption. This allows it to identify unusual current distribution and potential contact issues that could contribute to connector damage. The device can also provide visual and audible warnings when configured limits are exceeded, with an optional automatic shutdown function.

"One of the most common points of feedback, however, was that the fan could still be noticeable in very quiet systems, so working with Noctua on a significantly quieter cooling solution was the logical next step - and, for us, really completes the product," added Hartung. For the Noctua Edition, the standard cooling solution has been replaced with a customized design featuring a Noctua NF-A4x10 fan, an optimized fan grille, and an enlarged CNC-machined aluminum housing. The fan uses semi-passive operation, remaining off for longer periods and only spinning when additional cooling is required.

In a worst-case scenario with the case fans turned off and temperatures above 40°C, it could handle up to a 300W GPU load without turning its fan on. When it does need active cooling, its fan runs under 2,000 RPM compared to 5,000 RPM on the standard mode, which cuts down noise from 39.4dB(A) to just 21.5dB(A) at a 10cm distance. This should make it essentially inaudible alongside the other fans in a very quiet PC.

The WireView Pro II Noctua Edition is available in Normal and Reversed variants to accommodate different 12V-2x6 connector and cable-routing configurations, along with an extended two-year warranty covering the GPU connector. While the press note suggests a retail price of $189.90, it is currently selling at $222.18 on Thermal Grizzly’s official online store.

Game streaming over your local area network is cool, but game streaming as typically implemented is basically a hack. It borrows video streaming technology and applies it to interactive games, which isn't actually a great fit, like so many cases of using a tool for a task it wasn't really designed for. Legendary open-source dev Hans-Kristian "TheMaister" Arntzen (known for the libretro framework and Retroarch frontend), decided to tackle this problem by making a video codec called Pyrowave specifically designed for in-home game streaming, and now, that exact codec is implemented in the Steam beta client.

Your LAN has less than 10 milliseconds of latency; less than one millisecond if it's wired. However, in-home game streaming rarely achieves latency anywhere close to that because the process of rendering the game, encoding a video, sending it over the network, and then decoding it (before you can even see the new frame and react) usually takes upwards of tens of milliseconds, meaning that even on a LAN it's possible to have noticeable input lag when streaming.

There are also possible compromises on image quality for in-home streaming. Typical video codecs like AVC and AV1 rely on a lot of "tricks" to reduce how much real data they need to use to encode a video stream; one of the most common is chroma subsampling, where a video uses less data to represent the colors in a scene, because human vision is much less sensitive to brightness than color. This is fine for a lot of games, but it can cause problems on the desktop as well as in games with lots of text (or similar fine elements), because the text develops nasty fringing that makes it hard to read. You can solve this by using 4:4:4 video, but that's actually not very well supported by common video codec hardware.

Arntzen's Pyrowave solves both of these problems (latency and quality) by working in a fundamentally different way from other video codecs. Instead of using Discrete Cosine Transforms and inter-frame encoding, Pyrowave is similar to Motion JPEG2000 and uses Discrete Wavelet Transforms along with intra-frame encoding. There are a lot of downsides to this approach, but a lot of upsides, too. You get very consistent quality from frame to frame (making it perfect for constant bitrate applications) and you also get excellent error resilience. Because Pyrowave is very simple and computed on the GPU's shader array rather than the video engine, which doesn't understand it, you also get insanely low latency, and there are no concerns about the capabilities of fixed-function hardware.

The downside? Well, it's in the headline: bandwidth. In the Steam beta client patch notes where Valve announced the addition of this feature, Valve notes that the codec uses "5-10 times the amount of bandwidth of other streaming codecs." So how much bandwidth is that, really? In a brief test of Phantasy Star Online 2: New Genesis, streaming to a Lenovo Legion Go S from a desktop, we clocked Pyrowave on default settings at about 210 megabits per second. That's over 26 megabytes per second of video going down the line, which is an incredible amount of data to be sending over a network so you can play a video game in bed without sacrificing visual quality or frame rate.

But most notably, it was tangibly more responsive than the usual Remote Play experience, and best of all, the image quality was quite exceptional, especially once we ticked on the 4:4:4 mode. Unfortunately, we weren't able to see if the GPU overhead was overbearing with an RTX 5070 Ti and frame rates capped at 120 FPS for streaming.

Just for clarity's sake, while it's possible that Pyrowave streaming could cause service interruptions for other people on your LAN (and thus isn't suitable for high-traffic networks like at a company or large business), it is strictly intended to be used over your local network, not the Internet. As a result, your internet connection doesn't matter at all, so if you were worried about ripping through your data allotment on a metered connection, there's no need for alarm; all of the data sent is between devices on your network. Even the over-200 megabits-per-second of Pyrowave is peanuts compared to the tens of gigabytes per second your graphics card is sending to your display via DisplayPort or HDMI, after all.

If you'd like to test out the Pyrowave codec yourself with Steam Remote Play, you'll need to be on the Steam beta client first. After you swap to the beta client, go into the Remote Play settings and you should see the option for Pyrowave. It's currently only available for standard games (i.e. not VR) on macOS, Windows, and Linux, although Valve says it's coming soon to the Steam Link app for mobile devices as well. You'll need "at least Gigabit Ethernet", although user reports in the Steam discussions say that it works fine on a solid Wi-Fi 6E or Wi-Fi 7 connection, too.

Following the reveal of OpenAI’s Jalapeño ASIC, a clear question formed: Who is this for? That’s not to say the accelerator doesn’t have a purpose, but rather that OpenAI didn’t clearly define what its ambitions were in the hardware space. On one hand, the company suggested it was building ASICs for its own purposes when OpenAI and Broadcom revealed their partnership last year. On the other hand, OpenAI laid out benchmarks comparing Jalapeño to Nvidia’s Blackwell accelerators and doubled down on a multi-generational roadmap at Hot Chips 2026. Jalapeño is built for OpenAI’s compute needs, Richard Ho, Head of Hardware at OpenAI, told Tom’s Hardware Premium. However, the VP says “you could use it for anybody, honestly,” and left the door open for a wider rollout. You can read the full transcript of the interview here.

“We have such a strong demand for compute within the company. It's going to take us a good long time to even fill our own demand, which is growing all the time,” Ho said. “I think that we're going to have our hands full just providing compute for OpenAI for a good long time. That's not to say that it can't be used elsewhere. I believe it could be, but I think our priority is to make sure that OpenAI's compute needs are met first and foremost.”

The competitive positioning of Jalapeño mainly comes down to the benchmarks OpenAI shared during Hot Chips, run on SemiAnalysis’ InferenceX benchmark and comparing Jalapeño to Nvidia’s GB200 and GB300. ASICs are common, but competitive performance for them isn’t common, and for good reason. They’re built to accelerate specific workloads. With Jalapeño, however, OpenAI demonstrated the chip accelerating its own open-weight GPT-OSS model, as well as DeepSeek R1 and Kimi K2.5.

Originally, OpenAI didn’t plan to show benchmarks at Hot Chips, and the company wasn’t sure if it would present at the event at all, Ho told us. The executive reiterated the story OpenAI told on the Hot Chips stage, about how a team of engineers got Kimi and DeepSeek up and running on Jalapeño in the two months between the A0 sample and the Hot Chips presentation.

Although Ho was clear that Jalapeño is being deployed internally and will remain internal for the time being, he certainly left the door open to a wider entry into the hardware market. Speaking on the benchmarks shown at Hot Chips, Ho said: “What we really wanted to demonstrate, to put to rest, the misperception in the industry that our custom inference chip was only for OpenAI models… It’s programmable, and it’s general purpose, and it’s not hard-coded for OpenAI models.”

One possible explanation for reluctance to enter the external hardware market is supply. Ho said “there’s a new baseline for supply,” referring to the past two years of Ho and OpenAI CEO Sam Altman touring fabs and asking for more capacity. Although Ho says “[OpenAI is] in good shape” on the supply front internally, supply to feed external customers is likely a different story.

Jalapeño works for other models, but raw competitive performance wasn’t the main design goal. When I asked about the driving force behind designing Jalapeño, Ho was blunt: “It was efficiency.” The executive pointed to efficiency as a cousin of compute, noting the power-constrained modern AI data center and how a more efficient inference engine represents more effective compute.

Ho also pointed to that same pragmatic decision-making as a driving force behind designing Jalapeño, notably around codesign with OpenAI’s internal models. “[Codesign is] something that you can’t do with a third-party silicon merchant really well because there’s a lot of research IP in the models, and so you just can’t share that widely because it will leak. It will get out there no matter how many NDAs you put in place.”

If Jalapeño were destined for a wider rollout, it wouldn’t be going up against Nvidia’s Grace Blackwell platform, but the newer Vera Rubin platform. Ho said that the comparison against Blackwell was “because those were the best published results that we could find.” However, the company has run more benchmarks internally, both against Vera Rubin and for larger context windows.

The InferenceX benchmarks only looked at 8k1k benchmarks, which represent a fixed 8,000 input tokens and 1,000 output tokens. Ho said OpenAI’s internal benchmarks show that the ASIC “seems to perform even better than the existing benchmarks from some of the other devices that are available.” More interesting is the comparison to Vera Rubin, which OpenAI says looks good.

“Obviously, but the time we deploy, it’ll be [Vera Rubin], maybe even VR Ultra in some parts of the deployment schedule. We’ve done our internal ones, but obviously we don’t publish those. Those have to come from Nvidia and other people who are able to do that.… yeah, we’re doing really well on those,” said Ho.

OpenAI revealed its Jalapeño inference ASIC at Hot Chips in August 2026, a chip that leaned heavily on AI to deliver an incredibly short design window. Following the reveal, Tom's Hardware had the opportunity to sit down with the company's VP of Hardware, Richard Ho, to answer some of our most pressing questions about how the chip came into existence, future ambitions, and how AI might be used in the development of silicon.

The following article is a full transcript of our interview with Richard Ho, which has been edited for flow and clarity. You can also read additional interview transcripts we produced earlier in the year, featuring Intel, AMD, Nvidia, Valve, and more. This transcript is free to access for a limited time as part of Tom's Hardware Premium's AI Chip Design Week.

Jake Roach, Senior CPU Analyst, Tom's Hardware: It was quite the ending to Hot Chips when you dropped this. I want to start at a high level. There are a lot of reasons for OpenAI to develop its own ASIC, but was there one thing that you could point to more specifically that was a driving force? Whether it’s performance, efficiency — what was it that really drove that decision?

Richard Ho, VP Hardware, OpenAI: It is efficiency. I think that’s the main thing that we’re aiming for, because obviously, as Sam [Altman] has been saying, we are going to be compute-limited, and a compute limitation is really how much power we can get into data centers.

What we want to do is be as efficient as we can with the limited compute and limited power that we’re going to be able to get, and make the most of it. Because what we really care about is how much intelligence we can deliver to the users, and having a more efficient inference device is very useful. That’s why we focus on inference, because training happens, and you do a lot of compute with the pre-training, but really the cost to the user is on the inference side, and their perception of intelligence is going to be there. Their user experience in terms of how fast ChatGPT responds, or how fast Codex responds, or how fast the agents respond — the latency really matters.

You can see all of those things in the ingredients of what we announced. You can see that we have both a very good low-latency device for those who really care about it, and we can very easily just turn the knob and get very good throughput, so you can reduce the cost of that inference. Really, that’s the thing that we were aiming for. I’m very happy that the team managed to deliver that.

The benefits of building in-house

Roach: Developing your own ASIC versus going with something that’s currently on the market— were you just not satisfied with the efficiency of current offerings?

Ho: Well, I wouldn’t say that. The way to really think about it is we wanted to take advantage of the co-design opportunity that we had. It’s something that you can’t do with a third-party silicon merchant really well, because there’s a lot of research IP in the models. You just can’t share that widely because it will leak. It will get out there no matter how many NDA’s you put in place.

Ho: Having an internal team being able to work with our researchers, who are able to have full visibility into the full stack, and take care of that: “Should we do this in the software? Should we do it in the model? Or should we do this optimization in the hardware?” We can make those trade-offs intelligently because we have that full visibility, and I think that’s where it comes from.

A lot of the benefit of Jalapeño is that visibility that we had and [we were] able to see exactly what hardware was needed to make those trade-offs. Be intelligent, put whatever we need to put back into the compiler, back into the stack, but really make the hardware fly for this particular application here, which is the outcome of this full-stack co-design opportunity of being inside OpenAI.

Roach: I did want to clarify some points here, because there’s been various quotes floating around about optimizing for this specific workload, and I think that has been maybe misattributed to optimizing specifically for OpenAI’s workloads.

Ho: Yeah, it’s misattributed. The whole point of using the InferenceX benchmark from SemiAnalysis was that it was (using) open-source models, and they’re different models. The architecture is different, and their sizes are different. What we really wanted to demonstrate, to put to rest, the misperception in the industry that our custom inference chip was only for OpenAI models — we’ve shown with the Hot Chips results that it flies on open-source models, flies on any LLM, in a sense. All transformer-based LLM models will be very performant.

The thing we also wanted to show was just how easy it was to program. Taking these models, which we did not even look at until after we got the chip back, and getting them up and being performant in two months, roughly, and being able to present the results, shows it’s programmable, it’s general-purpose, and it’s not hard-coded for OpenAI models.

Roach: It leads me to wonder: Jalapeño is obviously for OpenAI’s inference workloads. Is that all it’s for, or are you considering external customers? What is the plan with OpenAI hardware?

Ho: You could use it for anybody, honestly. But we have such a strong demand for compute within the company. It’s going to take us a good long time to even fill our own demand, which is growing all the time.

With the growth of the daily active users and weekly active users, with the new models, with the new capabilities of Codex, and all the other reasoning things that are going on — and there’s new announcements coming that [are] not out yet, but we kind of know internally — I think that we’re going to have our hands full just providing compute for OpenAI for a good long time. That’s not to say that it can’t be used elsewhere. I believe it could be, but I think our priority is to make sure that OpenAI’s compute needs are met first and foremost.

Inside the tools and timeline

Roach: Moving to the timeline, it’s remarkable that — what, nine months, I think it was, to initial RDL the tape-out? Really remarkable. Assisted by AI. Does that get faster? Is this kind of ground zero of what we can do with an AI-assisted design process? Are you able to move quicker as you ramp up your roadmap?

Ho: The way I like to think about it is, we’ve established a new baseline. In the old baseline, you’re talking 18 months to two years, roughly. Often that’s even with some existing IP or some more legacy architecture design. We’re starting from scratch here. We had nothing. There’s not a line of code here to refer to.

What we’ve established is that there’s a new baseline that you can do with a very talented team with the help of AI. Now, does it get shorter? It depends on what you’re trying to do.

With Jalapeño, we made some, I consider to be, smart and pragmatic trade-offs on the architecture, the microarchitecture, to hit a very fast time to market because the compute need was so high. It’s like, “Okay, how fast can you get this device for us?” There were some pragmatic trade-offs.

If you were to make a much more complex device — and technology is coming along, with 3D stacking, with co-packaged optics, and stuff like that — will it take longer? Will it take nine months? I won’t say it will take nine months. I think it will go faster than if you didn’t have AI models. If you’re doing a derivative design of Jalapeño, it should go much faster than that. We should be able to do that really, really fast.

What we’re saying is that I think we’re establishing a new baseline: nine months from scratch. Then you’re going to have your usual engineering ups and downs from there. But we think that every engineering team in chip design should be able to use this as a new baseline, because it’s a proof point that the models that are in use — the AI models for us is mostly Codex, Sol, the one before Sol, and now we’re moving on to Astra. These are super capable.

Even from when we started that work, back in November 2025, to when we taped out, the models improved enormously. Even from that moment to when we started doing the kernel optimization in May, when the chips were first coming online, we ourselves were shocked at how much better Codex was and what it could do.

I’ll be honest with you: We were actually a little bit surprised at the performance we were able to squeeze out in those two months of sprinting on the benchmark, because we just didn’t realize just how good the models were at doing kernel optimization.

That’s something that everybody can learn from, to be honest. It’s a proof point that it can be done. This is how AI should be used. We didn’t replace our engineers; they just became super productive. With a smaller team of really good engineers with a lot of this AI stuff, you could do things faster and better than you could otherwise. I think that’s a good model of how engineering should be approached in the AI age.

Roach: I appreciate that insight. I know for at least some of our readers at Tom’s Hardware, the idea is, “Make me a CPU” in ChatGPT, and then it spits something out. But obviously, a lot more has gone on.

During the development process, are you using standard EDA tools from Cadence and Synopsys? And where are those?

Ho: I think this is super important. In general, my team is very open-source-pilled in many ways. We actually put stuff back into open source, and we were open-source-pilled before we got here.

But for sign-off, you need to use the standard EDA flows, and we did, because you want to make sure those results are good and correct. There’s no real alternative today. Part of it is this combination of standard flows optimized with AI, optimized by really good engineers.

Interest from the wider industry

Roach: Obviously, you guys work with hardware vendors across the industry. I’m curious if you’ve had conversations with them post-Jalapeño reveal about this AI-assisted process, and if you’ve heard anything from them.

Ho: Yeah, we engaged with them before the reveal as well because we knew the results were there, so we started talking with some of them. Post-review, we did get a lot more communication with them.

I’m not going to preempt anything here. I can tell you that there’s a lot of interest in the industry, and I would also tell you that we feel that there is a lot of benefit in industry generally that we want to enable.

This is not something that, “Hey, we have this, and we’re going to keep it to ourselves.” It’s not one of those things. We want to make the industry more productive in general because better compute from everybody helps us as well, and so we want to make sure everyone gets it. I think that’s something that we’ll see more about quite shortly, to be honest.

Roach: Just to clarify, when you’re saying you’re seeing interest from the industry, that is for the design flow, how you built the chip, not necessarily, “Hey, we’re going to throw out a bunch of Jalapeños to everyone.”

Ho: Right, exactly. What we did to make those timelines, what we did to get the performance boost at the end. How did we do it? What did we use? I think those are learnings that we want to bring out to the industry as well.

As you probably are aware, there is a pretty active startup scene around AI for chip design, and it’s good. There’s a lot of smart people thinking about it and trying to do it. We have our take on that, and I think at some point we want to tell the world, “Here’s our take on it.”

Fundamental to that is Codex and GPT-6 Astra coming out. Those are fundamental, and we can basically point to it; it’s not going to be slideware or vaporware. We can point to it and say, “Here’s what we did, here’s how we did it, and here’s what we got.” It’s going to be very concrete.

Roach: So it was a proof of concept that ended up being quite a bit faster than expected?

Ho: Yeah. To be honest, the way it worked — and I’ll give you a little bit of insight — our engineers were just like, “Oh, we have these models, and they’re kind of cool. Should we try them?”

They tried them. There was no real “This is what we’re gonna do, and here’s how we’re gonna do it.” They just tried it at a grassroots level. Then they’re like, “Oh my God, it’s so good. Hey, come over here, have a look at this.” Then slowly the whole team got, “Oh man, this is really useful and really good, and here’s how we’re gonna do it.”

The researchers helped us. The researchers we have in the company helped us when we ran into some, “Oh, it doesn’t quite do it this way,” and we’d ask them, “Is there any way we can fine-tune it or something like that?” Then they would come back with replies.

It was really a collab between the chip team and the research team. We do sit with them. The chip team is actually considered part of that research-adjacent organization here within OpenAI. The collab has been really close, because that’s how we got the co-design to start with.

But then this part was almost a bonus. We didn’t set out necessarily to do this as a target for what we did. It just turned out that, “Oh yeah, this is really useful.” The engineers loved it, and now we have a way to do this.

Roach: I want to zoom out a little bit here, because one of the concerns with everyone right now is supply, just in general. Not only supply, but even space to do anything. Where are you with that? I’m assuming you’ve anticipated this situation and have secured your supply.

Ho: It’s a hard situation because supply is very limited. I don’t want to say, “I told you so,” but two years ago, Sam (Altman) and I were doing a tour around all the different fabs and suppliers. I went to say, “Please, please, please build more, build more. We’re gonna need it.” And they were like, “Hey, trust us. We’ve seen the cycle before.”

But I think it’s now become evident to everybody that, just like we were talking about, there’s a new baseline for how to do chip design. There’s a new baseline for supply and what we need in terms of memory, in terms of logic wafers, in terms of all the rest of the components that go into it, SSDs and everything else. The supply chain is responding, but it takes years to get that going.

We’ve seen this for a while, and so we’ve been active in trying to make sure that we have our supplies established and set up. We think we are in good shape for that.

Using Turing over Vera, and OpenAI's north star

Roach: I cover chips broadly at Tom’s Hardware, primarily focused on CPUs. We have someone who focuses more on graphics, and it was interesting to me to see — I was reading the SemiAnalysis article about it, about the Turing rack that goes alongside a Jalapeño rack.

What was the decision there for Turing and not Vera? I would have expected, given the close working relationship between Nvidia and OpenAI over the years, I would have expected Vera. What makes Turing the right fit?

Ho: The way we approached that design was really in terms of de-risking and being able to do that design fast. Vera, as a standalone, is a little bit behind on that maturity level. The Turing device is strong. It did what we needed to do, and partly our partners had some experience with it.

It wasn’t necessary for us to take a huge risk on that, and so we didn’t. As I said earlier, for the Jalapeño program, we were trying to make very pragmatic decisions. We wanted to be aggressive on the goals of the performance and the cost, but we didn’t want to take unnecessary risks. That felt like a good design decision that would fit within the parameters of how we make these design decisions.

Roach: I’m curious internally: Is the scope of Jalapeño right now — you have a huge compute need. It may not even be able to satiate that. Would the idea be, “Hey, if we can run everything on our own accelerators one day, that’s great”? Is that the ultimate pie-in-the-sky goal?

Ho: I think the ultimate goal is to use the best device in terms of performance and cost. If it turns out that it’s our own internal device because we can do the co-design, because we can do the rest of it, and we then get the performance benefit per watt, then yeah, let that be the case.

But if it’s not, if there is another chip that’s provided by a silicon merchant or another partner, I’m more than happy to put those in the fleet. Our goal is to lower the cost of infrastructure. That’s what our goal is. Whatever the best way to do it is, we’ll do it.

Now, we’ve taken a bet that we can do better than merchant silicon because of this co-design benefit, and it seems to be paying off with Jalapeño. Will it continue paying off? I believe so. But am I going to say that’s our north star? No. I’m going to say our north star is the lowest cost of infrastructure we can get.

Roach: I wanted to ask you the question because I know we’re going to get comments about, “Oh, they’re still using Nvidia. They’re still using AMD.” Obviously, you guys use everything at this point.

Ho: We use everything at this point. But as you know, it’s a constant — you can’t imagine — it’s a constant evaluation. We’ll constantly be evaluating as we continue to deploy, and so the ratios might change.

But as long as we keep that North Star in mind, what is the best device, and not have this attitude of, “Well, we built it, so it has to be there” — and that’s not the way we think about it — then I think we’ll be doing the right thing for both ourselves and our end customers.

Speculative decode and performance on Jalapeño

Roach: Drilling down a bit more into the technical weeds — I know we’re running up close here — speculative decode is currently not implemented on Jalapeño. Do you plan to implement it on Jalapeño?

Ho: It’s implemented in the hardware. The only reason we didn’t benchmark it is that we didn’t have the time to train those draft models to do the speculative decode with Jalapeño. We have internal models that do it. That’s the only reason we did that benchmark again.

Just to give you the background on that one. We did not plan on doing this benchmark until after we got the chip back. We saw it was working; it was working really well. They said, “How are we gonna tell the world about this?” And we said, “Oh, that benchmark. Let’s go for it.”

It was crazy. It was two months until the paper deadline — the presentation deadline. Just like, “Can we do that? And how many of these models can we get done?” We just went for it, and we said, “Well, there’s no time to do the multi-token prediction, but hey, it looks like our single-token prediction might be better than the multi-token prediction. So let’s just publish those results, because that gives you an indication.”

The multi-token prediction is going to be 3-5x performance. That’s in our pocket. We have that available, and we’re going to roll that out in our own models. When we put it into production, we’re going to have that available.

But it didn’t seem necessary to do that for the benchmark, because if your single-token prediction is better than the current state-of-the-art multi-token prediction, you know that your multi-token prediction is going to be much better. That was the reason behind that.

Roach: So you’re saying you get the chip back. You have two months. You weren’t even planning to show off benchmarks originally?

Ho: No. The Hot Chips organizers were actually very flexible and nice. They asked us, “Do you want to present this year?” And we said, “We’re not sure. How late can we tell you?”

They had this last slot, and they kept it there. And if not, the program would have just ended earlier or something like that. Then finally, very late, after we got the chip back, we were like, “Can we have it?” And they said, “Yeah, go for it.” And we went for it.

Roach: Another question I had is looking at longer context windows. If I’m not mistaken, all of them are 8K/1K on the SemiAnalysis InferenceX benchmark. I know you haven’t shared those. I’m assuming you’ve looked at longer context windows internally.

Ho: Yeah, internally, of course. Like we said, I think we said this somewhere in one of the slides, is that on internal models, the gap gets even wider. Yes, with longer context, with even bigger models, Jalapeño seems to perform even better than the existing benchmark from some of the other devices that are available.

I would also highlight that we did a lot of comparisons against Grace Blackwell, but that’s because those were the best published results that we could find. Obviously, by the time we deploy, it’ll be Vera Rubin, maybe even Vera Rubin Ultra in some parts of the deployment schedule.

We’ve done our internal ones, but obviously we don’t publish those. Those have to come from Nvidia and other people who are able to do that. We won’t publish those results ourselves.

Ramping and the future

Roach: I believe this is right — Jalapeno has a slow ramp-up through the rest of the year, but 2027 is when the ramp really...

Ho: 2027. Yeah. I think we want to get some amount in there if we can, a very small volume, just to make sure that everything’s working well and we can test in the production environment. Then 2027 is when the ramp is going to really show up.

Roach: Going back to your roadmap here, you wanted to set a new baseline. You’ve obviously announced two more generations [...]Gen 2 is approaching tape-out. Is that the same cadence moving forward? Is it around Hot Chips next year when we should expect to learn more about Jalapeño 2?

Ho: Let me be clear about that. I’m not of the opinion that you should just tape out on a calendar schedule.

We want to tape out when the device that we have in mind makes some kind of step-function improvement in some way, like performance per watt, raw or latency. A lot of that is dependent on when technology becomes available.

Whether it be which generation of HBM you’re using, which type of SerDes you’re using, or whether you can get optical communication closer to the silicon. Our projects and tape-outs will be dependent on the maturity level of the technologies.

We can do very fast execution. Will we do those types of executions back-to-back? I doubt it, because the technology will not be ready for that, and I don’t want to tape out something that is 2% better than what I taped out before, because it’s not worth it to change a fleet. But what I’ve been seeing is the technology does improve at a cadence which is pretty reasonable, and we’ll be able to do our execution fast within that.

The most important thing is building the right device. You've got to spend enough time to build the right device. Know what that device is. Then when you build it, just build it fast. Get it out as fast as you can.

But you need to spend enough time to know what’s the next best device, and it’s not just a routine on the treadmill type of thing. That’s the thing I don’t think we want to be on the treadmill for, just for the sake of it. We want to really make a step improvement with every device we do.

Roach: One of the most interesting slides to me is really early in the presentation, where you’re listing out goals, and not only goals, but you listed out the non-goals. I thought that was really telling, because you got to define what you’re not trying to do.

Ho: Exactly. We want to be very thoughtful about our program here because we are a very small team. The things that we do, we want to make a really high impact, and the impact is for the north star: enabling more intelligence, more cheaply for our customers. That’s the thing we’re trying to do.

We want to be very thoughtful about what it would take to do that. As I said, if something can be provided by the ecosystem, and we can’t do better than that, then we just take the ecosystem.

We’re going to always do something that we think is taking advantage of our co-design, taking advantage of our knowledge of where things are going, and being able to use that intelligently.

[Session Ends]