Google was among the first hyperscalers to develop its own custom AI processors about a decade ago and has been steadily ramping their deployment since then. The company seems to be so confident about its TPU v9 due in 2028 that it intends to order 12 – 15 million of such processors, according to a Fubon Research note to clients published by Sean. If the information is correct, Google may not only produce more or a comparable number of AI accelerators than Nvidia, but may also need to use Intel Foundry to meet its goals.

"Based on our checks, Google plans to have 12 – 15 million TPUs in 2028," the paper reads. "Entering 2028, Google’s TPUs will enter the V9 generation with four compute dies, suggesting that their capacity consumption will more than double in 2028 versus 2027."

Fubon estimates that Nvidia supplied 8.2 million data center AI GPUs in 2026 and is on track to increase the number to 12.4 million in 2028. If Fubon is correct about Google's plans to produce 12 – 15 million 9th-generation TPUs in 2028, then the company may produce more, or at least a comparable number of AI accelerators, than Nvidia in 2028.

TSMC is not enough

How the performance of Google's v9 TPUs will stack against Nvidia's Rubin and Rubin Ultra is something that remains to be seen, but the fact that Google intends to use four compute chiplets on these AI accelerators clearly points to the fact that the company bets big on the performance of these processors. Meanwhile, building an AI accelerator with four large compute chiplets is a major engineering effort, which Google seems to have accomplished.

"Although we do not have the detailed allocation yet, we think it is difficult to reach Google’s target with TSMC alone, and Intel's supply is a must by 2028," the paper continues.

Researchers from Fubon are not sure whether Google's allocations at TSMC will be enough to meet the company's demand for 12 – 15 million 9^th Generation TPUs, so they think that Google will have to use Intel Foundry's capacity to meet its volume goals. Over the past few months, we have seen reports claiming that Intel had landed orders to make three million TPUs for Google following months of Google's testing of Intel's advanced packaging technologies. Indeed, if Google wants to make its silicon at Intel Foundry, usage of Intel's advanced packaging services makes great sense. It should be noted that when compute chiplets are developed, they must be developed with their packaging technology in mind, as Intel's EMIB/EMIB-T and TSMC's CoWoS-L are incompatible.

World's largest consumer of AI accelerators

If the information about Google's plans to produce 12 – 15 million TPUs in 2028 is correct (note that the difference between 12 and 15 is 20%, which is huge) and Google will indeed deploy more AI accelerators annually than Nvidia sells to the entire market, it would mark a dramatic shift in the AI hardware landscape. It will not only make Google the world's largest consumer of AI accelerators (as the company will unlikely cease buying Nvidia hardware), it will eventually make Google the owner of the world's most capable AI hardware fleet. Whether or not Google will use its overwhelming AI compute capacity primarily for its own services, or will lend the majority to other is something that remains to be seen.

Meanwhile, for Google's rivals, the milestone will underscore the growing importance of vertically integrated AI infrastructure, where cloud providers design chips tailored to their own software stacks, workloads, and data centers instead of purchasing off-the-shelf GPUs.

Yet, Google's surpassing Nvidia in unit shipments would not necessarily diminish Nvidia's dominant position. AI demand continues to expand so rapidly that both companies could increase deployments simultaneously, but Google will simply grow faster, at least till Nvidia ups production of its AI accelerators with Feynman and Feynman Ultra in 2029 – 2030. After all, Nvidia's AI GPUs are sold out. What Nvidia should worry about is not the volumes of TPUs that Google can deploy, but rather the fact that these processors do rely on a software stack that rivals Nvidia's CUDA, the company's main competitive advantage.

After granting about a dozen manufacturing licenses to make various x86 CPUs back in the 1980s, Intel ceased to license both its cores and instruction set architecture (ISA) in a bid not to create rivals. However, in an unusual turn of events, Intel has quietly granted startup RosaicLabs access to its Atom processor technology, reports Reuters. The company was incorporated in May and is led by Lip-Bu Tan's co-investor.

Intel provided Rosaic access to an unknown Atom-class core, which enables the company to build its own custom processors based on x86 general-purpose cores, according to the report. The renowned chipmaker plans to ship Rosaic register-transfer level (RTL) code ​for the Atom processor core, which will let the startup build its custom system-on-chip (SoC) both at Intel Foundry and elsewhere.

The startup is reportedly led by Amarjit Gill, a venture capital investor who partnered with Intel's CEO, Lip-Bu Tan, on multiple occasions in the past. The two invested in such companies as Nuvia and Rivos, which were later acquired by Qualcomm and Meta, respectively.

RosaicLabs does not have a website or a LinkedIn profile, which is common for startups when they operate in stealth mode. The company was incorporated in May and is currently seeking a seed funding round of $10 million, according to a document seen by Reuters.

Since RosaicLabs does not have a website or a LinkedIn profile, it is completely unknown what kind of SoC it plans to develop and which markets it is going to pursue. One could imagine that it is in Intel's interests to license technology to companies that seek to address markets which Intel has no plans to address.

Arguably the biggest question is which Atom-class core Intel licensed to Rosaic. Traditionally, Atom cores were developed for inexpensive low-power devices, applications that Intel ceased to address about a decade ago. Since then, the low-power x86 architecture has been used to build custom SoCs for telecom and adjacent applications, embedded CPUs, efficiency (E) cores for client CPUs, and more recently cloud-optimized Xeon processors. Intel's most advanced low-power x86 cores to date are Crestmont, which powers Xeon 6700E-series CPUs, Skymont, which is used in Core Ultra 2-series CPUs, and Darkmont, which powers Xeon 6+ CPUs.

Skymont and Darkmont feature a 9-wide decode, 8-wide out-of-order engine, and 16-wide retire, which makes them fairly capable cores that wed high performance potential with energy efficiency. Meanwhile, Darkmont is optimized for data center workloads, so it has better branch prediction, improved prefetch, an enhanced vector engine, and higher L2 bandwidth. By contrast, Crestmont features a 6-wide decode and an 8-wide retire, which puts it well behind the newer cores.

If Intel gives Rosaic complete, synthesizable RTL of an Atom-class core, Rosaic could technically modify the core at several levels, including changing cache sizes, reorganizing the pipeline, increasing clocks, and altering power-management logic, just to name a few options. However, this does not automatically mean Rosaic has unrestricted rights to enhance Intel's technology, as the company could provide RTL under various conditions with numerous restrictions. After all, it does not want to create a competitor for itself. Still, we do not know the terms of the license.

Intel granted about a dozen manufacturing licenses to build its 80286 and 80386 CPUs in the 1980s to various chipmakers in a bid to provide chipmakers with second sources for its processors and expand usage of its x86 ISA. However, only AMD got an actual x86 license that allowed it to build x86 CPUs of its own designs.

After disposing of its StrongArm/XScale business to Marvell in 2006, Intel witnessed the smartphone revolution essentially empty-handed as its Atom processors could not compete with highly integrated Arm-based SoCs in handsets. Intel tried to expand the reach of its low-power Atom CPU cores in 2009, so it signed a memorandum of understanding with TSMC and planned to port its Atom cores to a TSMC node and enable TSMC clients to integrate that hard IP into their processors.

That initiative has never taken off, so eventually Intel kicked off its SoFIA (Smart or Feature Phone on Intel Architecture) joint SoC development program that enabled third parties to use Intel Atom cores and modem technology (implemented using TSMC's 28nm node) in their application processors for handsets. While both Rockchip and Spreadtrum eventually came up with their SoFIA 3G and SoFIA 4G SoCs based on Airmont cores and made on TSMC's 28nm technology, both processors were released in 2015, had to compete against SoCs made on Samsung's 14nm-class node or TSMC's 16FFC node, and never got popular. Ultimately, Intel produced an eight-core Spreadtrum SoC at its fabs using its 14nm manufacturing technology, but that processor also failed on the market.

As a result, Intel licensing a CPU core to a third party is a very rare occurrence these days and the first in this decade. The reasons behind the move are completely unclear because the RosaicLabs startup is two months old, it cannot pay Intel cash, and its commercial prospects are completely unclear. While one may argue that now that Rosaic has access to x86 cores, it is not going to pursue Arm or RISC-V cores, keeping in mind that hundreds of startups choose Arm or RISC-V every year, addressing one startup does not enable Intel to expand its x86 share compared to Arm or RISC-V tangibly.

In any case, for now, the deal between Intel and RosaicLabs leaves more questions than answers, mainly because all we know about RosaicLabs is that it is led by an old acquittance of Intel's chief exec, Lip-Bu Tan.

Seagate is on track to start qualification of its hard disk drives featuring 50TB-class capacities in late calendar 2027, with shipments to follow in 2028, the company announced this week. Demand for HDDs is so strong because of the rise of AI and continued strength of the cloud computing business that most drives are sold out through 2028 and negotiations about allocations for 2029 are ongoing.

"Mozaic 5, our 5+ terabyte per disk platform, remains on track for qualification shipments in late calendar 2027," said Dave Mosley, chief executive officer of Seagate, during the company's earnings call with financial analysts and investors.

Mozaic 5 is the company's 3^rd generation platform for commercial hard drives based on Seagate's heat-assisted magnetic recording (HAMR) technology that succeeds Mozaic 3 and Mozaic 4. The Mozaic 5 platform enables the company to build platters with over 5TB capacity and consequently build 10-platter HDDs with over 50TB capacity featuring conventional magnetic recording (CMR) for clients seeking performance and versatility or shingled magnetic recording (SMR) for clients that need maximum capacity to maximize their storage density.

If Seagate preps to initiate 'qualification shipments' of its 50TB-class hard drives in late calendar 2027, then it means that by the time the HDDs have passed all the manufacturer's internal validations, including reliability and durability of heads and media, shock and vibration tests, and longevity tests among many others. It typically takes server OEMs about two to six months to qualify new HDDs for their offerings, whereas hyperscale cloud service providers usually qualify them for six to 12 months. In any case, it is safe to say that Seagate is on track to ship 50TB-class hard drives in calendar 2028 with significant volume ramp in 2029.

These 50TB-class HDDs will come to market just in time to meet exabyte demand from the AI and cloud sectors. Most of Seagate's nearline HDDs have been allocated for 2027 and 2029 under long-term supply agreements (LTAs), with some customers looking to secure supply in 2029.

"Based on the long-term supply agreements in place today, the vast majority of our nearline exabytes are now allocated into calendar 2028," Mosley said. "[…] As our strategic relationships deepen, many are actively seeking to extend planning horizons through 2029 and beyond, which we believe reflects growing confidence in their own long-term infrastructure needs."

Seagate's LTAs not only define exabytes, but also product configuration and prices. As it turns out, both are set for the 'entirety of calendar 2027.' Meanwhile, Seagate is flexible on pricing of drives that are not covered by LTAs as well as newly signed LTAs, so the company is implying price increases, following makers of 3D NAND and SSDs.

"We continue to execute our value-based pricing strategy, balancing a stronger demand environment with our objective of supporting sustainable, profitable growth over the long term," Mosley said.

"Our volume was a little bit higher in fiscal Q4," said Gianluca Romano, chief financial officer of Seagate, during the call. "We think can be maybe a little bit of output available in fiscal Q1. Of course, we are pricing that increased output at a very good price right now."

The key advantage of Seagate's high-capacity drives based on the company's Mozaic platforms is, of course, its HAMR technology, which is gradually increasing its share within the company's nearline HDD shipments. HAMR-based products accounted for a 40% exabyte share of Seagate's nearline HDDs as of early July and are on track to account for 70% of the company's nearline exabytes shipments by early July 2027. Moreover, nearly half of Seagate's nearline capacity will rely on its 40TB-class HDDs featuring its Mozaic 4 platform.

"We expect to achieve our next ramp milestone by exiting calendar 2026 with 50% of our HAMR exabytes on our Mozaic 4 platform," Mosley said.

For the fourth quarter of its fiscal 2026 ended on July 3, Seagate earned $3.629 billion, up from $2.444 billion it earned in the same quarter a year ago. The company's gross margin totaled 52.3%, up from 37.4% in Q4 FY2025, and its net income reached $1.294 billion. The company's FY2026 revenue was $12.195 billion, up from $9.097 billion in the prior year. The net income increased more than twice year-over-year to $3.184 billion, with gross margin reaching 45.6%.

Imperial Valley Computer Manufacturing has filed a lawsuit in a bid to gain access to Colorado River water, 287 million gallons of which it says it needs to cool a 330-megawatt data center, which would be the largest in the state. Despite only representing a fraction of the region's water supply, the buildout of the data center may affect the local farming and adjacent industries and terminate hundreds, if not thousands, of positions, reports Business Insider.

After two cities in the region denied the California-based AI data center recycled wastewater for cooling, it filed a lawsuit demanding to get water from the Colorado River for cooling. The 330-megawatt facility was not only designed to be the biggest AI data center in California, but it specifically committed not to use water from the Colorado River because it was promised wastewater. But now the owner of the data center is essentially asking to redirect water supply from agriculture to the facility.

Imperial Valley Computer Manufacturing — the owner of the 330 MW AI data center — is requesting access to approximately 287 million gallons of water per year after two cities — El Centro and Imperial — declined to supply reclaimed wastewater for cooling. The Imperial Irrigation District (IID), which distributes Colorado River water throughout Imperial Valley, also denied the company's request. The Colorado River supplies water to roughly 40 million people across seven western states and serves as the valley's sole freshwater source for roughly 180,000 people. Agriculture consumes about 80% of California's allocation from the river, while roughly 95–97% of the water IID delivers goes to agriculture.

The data center is seeking roughly 287 million gallons per year (about 750,000 gallons per day, or ~880 acre-feet per year), whereas the Imperial Irrigation District (IID) holds rights to approximately 3.1 million acre-feet of Colorado River water annually, which means that the data center demands only a small fraction — 0.028% — of IID's total water supply.

Sebastian Rucci, a Huntington Beach attorney who leads the project, claims that the facility's water consumption would be comparable to that of a 160-acre farm and will require no additional Colorado River allocation. In fact, he states that the facility would not increase pressure on the river because the company intends to purchase nearby farmland together with its associated water allocations.

Under the proposal, irrigation on those properties would cease, thus transferring the existing water quotas to be redirected to the data center cooling, at the expense of local farming output and associated jobs. "There's a lot of resistance in any agricultural community to 'buy and dry' because that's jobs," a senior fellow at the Pacific Institute focused on Colorado River Basin water use told the outlet. According to them, local resistance to the plan is less about the amount of water, and more about buying up farmland and reallocating it for industrial use.

The approach, of course, differs from the earlier plan that intended to avoid using Colorado River water altogether. However, after the data center was denied wastewater from two cities, it does not have a choice if it wants to go ahead with the buildout.

Rucci reportedly indicated that the project would provide substantial economic benefits for the local community, including 1,688 construction jobs, more than 100 permanent positions, and an estimated $2.95 billion in economic impact over 30 years. For a region where unemployment stood at approximately 17% in May, the economic diversification is essential. However, the big question is whether 100 permanent roles could offset the lost positions in the farming industry and industries tied to agriculture.

Water policy specialists interviewed by Business Insider said that the debate extends beyond the project's annual consumption. Instead, they questioned whether converting irrigated farmland into industrial use is an appropriate long-term direction for the region, which has historically depended on farming. The experts also warned that although landowners could benefit from selling land or water rights, surrounding rural communities may lose employment and business activity adjacent to agriculture, which includes equipment suppliers, repair shops, and sellers of fertilizers. Another factor mentioned by the experts was the U.S. reliance on farms around Imperial, California, and Yuma, Arizona, as they were the main suppliers of certain agricultural products in winter.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

The rogue OpenAI's autonomous AI agent that escaped its test environment and compromised Hugging Face remained unidentified as the attacker for about a week, according to a Reuters report that cites people familiar with the matter. If the information is accurate, this raises questions about OpenAI's control of its advanced AI systems and safety practices not only at OpenAI, but across the AI industry in general as autonomous AI agents are meant to work autonomously.

The incident began around July 9, when the autonomous agent allegedly attempted to break out of OpenAI's isolated testing environment, according to Reuters. Two days later, on July 11, it reportedly began infiltrating Hugging Face and the intrusion continued until July 13, according to Hugging Face co-founder Thomas Wolf. The report states that OpenAI did not recognize that its own system was responsible until after Hugging Face publicly disclosed on July 16 that it had been targeted by an autonomous AI agent. During the weekend of July 18–19, OpenAI investigators discovered evidence in internal logs, which proved that the agent escaped its testing environment, according to the report. By the time OpenAI informed Hugging Face, the repository operator had already reported the incident to the FBI. Then, on July 21, OpenAI publicly acknowledged the incident on July 21.

One of the reasons why it took OpenAI over a week to discover the breach is because OpenAI usually evaluates multiple advanced models simultaneously, which makes identification of a single rogue AI agent difficult due to enormous amounts of telemetry that such evaluation creates, according to Reuters.

Reuters claims the tested AI agent was designed for cybersecurity tasks and combined GPT-5.6 Sol with an even more capable unreleased OpenAI model. Before the breach, researchers had already observed unusual behavior during testing. In one case, an agent reportedly left instructions intended for future versions of itself that explained how to bypass OpenAI's internal restrictions. In other cases, it disabled monitoring mechanisms. Meanwhile, it is unclear whether these earlier events were directly connected to the agent responsible for the attack on Hugging Face.

Cybersecurity specialists interviewed by Reuters indicated that the incident exposes unresolved issues with the increasingly autonomous AI systems. Marley Smith of the World Ethical Data Foundation questioned whether OpenAI either failed to detect the agent's behavior or was unable to stop it, but argued that both possibilities are worrisome. Jeffrey Ladish of Palisade Research said the case should prompt scrutiny not only of OpenAI, but of whether leading AI developers are willing to invest sufficiently in security as they tend to deploy ever more capable models. He added that government oversight may ultimately be necessary though he did not describe how could the government oversee the very dynamic industry without slowing down its progress.

Nvidia and SK Group this week signed letters of intent to formalize their new strategic relationship valued at more than $500 billion. The strategic collaboration is multifaceted and includes a long-term memory supply agreement with SK hynix unveiled in June, SK Telecom's plans to build a 2-gigawatt AI data center based on the latest Nvidia hardware, and future expansions of AI infrastructure.

In addition to the multi-year memory supply and co-development agreement between Nvidia and SK hynix, the key part of the strategic relationship is SK Telecom's planned 2-gigawatt AI data center in South Korea. The installation will rely on Nvidia's DSX AI factory platform and deploy Vera Rubin accelerated computing systems equipped with SK hynix HBM4 memory. The first AI data center is set to enter service in 2027. The companies intend to use this infrastructure to support sovereign AI, enterprise AI, physical AI, and agentic AI deployments across South Korea and the Asia-Pacific region. In addition, the companies will work together on expansion of SK's AI infrastructure going forward, which is a rather vague way to say plans to deploy future AI platforms from Nvidia.

The most important part of the announcement is, of course, the gargantuan value — $0.5 trillion — of the intended strategic relationship. Based on what is disclosed, the figure is best interpreted as the aggregate value of commercial activity expected between the companies over several years, as it bundles together AI infrastructure construction and a long-term memory supply agreement under one umbrella. That activity likely will include the following:

• SK Telecom's purchases of Nvidia GPUs, networking equipment, systems, and other hardware for its AI data centers.
• Supplies of SK hynix memory to Nvidia under the long-term supply agreement.
• Revenue of Nvidia's ecosystem partners involved in building the DSX AI factories (OEMs, ODMs, networking, storage, cooling, power, etc.).
• Potential future expansion beyond the initial 2 GW deployment.

Speaking of the 2 GW AI data center, it is safe to say that it is going to use thousands of NVL72 VR200 racks and hundreds of thousands of Vera CPUs and Rubin AI GPUs. Unfortunately, this is as accurate as we can get with the rather vague announcement.

Nvidia describes DSX as a complete AI factory blueprint that combines its accelerated computing hardware, networking, software stack, and partner technologies into a data center-scale platform designed to deliver the lowest-cost token generation and maximum energy efficiency. Meanwhile, NVL72 VR200 will come with 166 kW – 240 kW per-rack power consumption ratings, whereas DSX can be deployed in various kinds of facilities with different power usage effectiveness (PUE). Since we do not know which NVL72 VR200 configuration SK Telecom plans to use, and since the PUE of the upcoming SK Telecom facility is unknown, it is impossible to estimate the number of racks and AI accelerators with any accuracy.

Intel on Thursday published its financial results for the second quarter of 2026, posting revenue of $16.1 billion — a 25% rise year-over-year — amid high demand for client and data center products. The company also said that due to extraordinary demand for its own CPUs, it will initiate mass production using its 14A (1.4nm-class) fabrication technology in 2028, which is in line with TSMC's plans for its A14 process technology.

"With encouraging external customer progress and increased demand for our internal products, we remain on track for 14A risk production for our internal products in the second half of 2027, and we made the decision in Q2 to fully commit to high volume ramp in 2028," said Lip-Bu Tan, chief executive of Intel, during the company's earnings call with financial analysts and investors.

Typically, companies initiate high-volume manufacturing (HVM) using a new process technology about a year after initiating risk production. Assuming that Intel intends to start risk production using 14A in the second half of 2027, it is reasonable to expect the company to start 14A HVM in the second half of 2028. It remains to be seen whether by the 'second half' Intel means July or December. If Intel initiates high volume ramp in November or December 2028, actual products made using the technology will emerge in 2029. In any case, Intel typically begins manufacturing using its leading-edge nodes in its development fab in Oregon and while it formally calls it HVM, actual volumes produced at such fabs are relatively low.

Another thing to note about Intel's 14A is that in 2028 it will start making its own products using this process, not products from external customers. Apparently, Intel still does not have any external clients that have committed to use the technology to make their products.

TSMC typically initiates production using its latest nodes in December and usually calls it the 'second half of the year.' Assuming that it follows the same pattern with A14 (though the progress of the node can enable the company to pull mass production in provided that customers' designs are ready), then the volume ramp will occur in 2029. TSMC claims that multiple customers have already taped out their ICs on A14.

Intel reported a strong second quarter as its revenue reached $16.1 billion, up 25% year-over-year and $1.8 billion above the midpoint of its guidance. Formally, Intel's GAAP losses reached a whopping $11 billion. However, this was driven by the $13.619 billion of mark-to-market losses on Escrowed Shares related to Intel's CHIPS Act Secure Enclave agreement with the U.S. government. Meanwhile, the company's non-GAAP net income was $2.2 billion, which reflects profitable underlying operations. The company's GAAP gross margin increased to 40.1%, up from 27.5% in Q2 2025. Intel's Operating cash flow totaled $7.0 billion, prompting the company to raise its capital spending outlook for both 2026 and 2027 as AI-driven demand continues to exceed available supply.

Intel's Client Computing and Physical AI Group (CCPG) generated $8.9 billion in revenue, up 13% year-over-year. The company confirmed that the CCPG result was not driven by increased unit sales, but was a result of higher average selling prices (ASP) due to supply constraints.

"Client obviously exceeded expectations. I would say it was largely ASP, of which some of that was mix related, some of that was our own like-for-like changes in ASPs where we thought we had seen some inflation on our cost and needed to pass that on to the end customer," said David Zinsner, chief financial officer of Intel, during the call.

The Data Center and AI (DCAI) business delivered the strongest growth as its sales climbed 59% year-over-year to $6.3 billion amid surging demand for Xeon processors, expanding AI infrastructure deployments, and rapidly growing purpose-built silicon sales.

"Q2 year-over-year server growth was the strongest on record, Xeon 6 continue to be one of the fastest ramping products in Intel history, reflecting improving execution and strong customer demand," Tan said.

"We also continue to see strong momentum in our purpose-built silicon product line, with revenue up roughly 20% sequentially and nearly tripling year-over-year," Zinsner said. "Purpose-built silicon revenue nearly tripled year-over-year."

Intel Foundry posted $5.8 billion in revenue, an increase of 31% year-over-year, as Intel 18A production ramped. At the same time the production units losses dropped to $2.1 billion — down from $2.4 billion in the previous quarter and $3.2 billion in the same quarter a year ago. External foundry revenue reached $293 million.

"Intel Foundry operating loss in Q2 was $2.1 billion and $348 million better quarter-over-quarter as higher yields improved cycle times and increased factory scale across Intel 4, Intel 3, and 18A drove improved wafer costs," Zinsner said.

Intel guided its third-quarter revenue to $15.8 billion – $16.8 billion and a projected non-GAAP gross margin of 42% and an EPS of $0.38.

AMD has announced its long-term CPU roadmap, including multiple generations of its Zen microarchitecture at its Advancing AI event. Much of the event was focused on the new 256-core EPYC 9996 sporting the Zen 6 architecture, as well as Venice-X, which is slated to arrive next year. But AMD also teased a Zen CPU roadmap going out to Zen 8.

"In 2028, we are going to introduce Florence," Lisa Su, chief executive of AMD, said. "Florence brings the next-gen Zen 7 cores and its leading-edge process technology. It's a new set of AI compute extensions to really ensure that we have all of the AI capability, and it supports the latest memory technologies."

Su did not disclose specific details about the process technology, core counts, memory subsystem, or AI extensions planned for (Zen 7) Florence. However, she indicated that Florence will not be a standalone processor family, instead joined by the Ferrara AI host node and Faenza Agentic Sandbox for different AI workloads. AMD says this approach will enable it to offer purpose-built CPUs for a wider range of applications rather than relying on a single architecture configuration across the entire server market.

"And we are not stopping there," Su said. "We are already deep in development of Ravenna, our 8th Generation EPYC family built on Zen 8, and that family is already well under development for 2030."

The CPU roadmap is part of AMD's general strategy to offer a predictable cadence for its data center platforms.

On the accelerator side, the company is developing its MI500-series Instinct products with next-generation HBM, larger scale-up domains, and new copper and optical interconnect technologies, similar to Nvidia's outlook toward Rubin Ultra and Feynman.

"MI500 will deliver the largest generational leap in the history of Instinct, putting us on track to deliver more than 2,000 times higher inference throughput in just four years," Su said.

AMD also confirmed that its CDNA Next-based Instinct MI600 family is already deep in development for 2028. At the event, AMD launched its MI455X GPU, as well as teased more about its upcoming MI500X range, which we expect to launch next year.

AMD and Cerebras Systems on Thursday announced plans to develop a platform that would combine AMD's EPYC processors in Helios rack-scale infrastructure with Cerebras' Wafer-Scale Engine (WSE) solutions. Together, the new systems promise to combine low latency of AMD's CPUs and Instinct GPUs with high throughput of Cerebras's Wafer Scale Engines (WSE) processors.

AMD and Cerebras expect the new inter-rack-scale platform — based on AMD Helios rack with EPYC CPUs and Instinct MI400-series accelerators inside — to be responsible for prompt processing and large context windows, whereas Cerebras' WSE will take care of the memory-bandwidth-intensive token-generation stage.

AMD and Cerebras expect their disaggregated inference platform to deliver up to 5X higher tokens per second per watt (T/s/W) by assigning different portions of an inference workload to architectures optimized for them. Therefore, AMD Helios provides rack-scale compute capacity and large volumes of complex requests, whereas the Cerebras WSE handles latency-sensitive token generation. The two compute platforms will operate within a single inference workflow, although the companies have not disclosed additional performance data or explained how the systems will be interconnected.

The underlying idea of the AMD + Cerebras platform is essentially the same as Nvidia's CPX concept, but AMD and Cerebras assign the specialized hardware to the opposite inference stage.

Nvidia's disaggregated design separates inference into context/prefill and generation/decode. The cancelled Rubin CPX GPU with GDDR7 was optimized specifically for the compute-heavy context/prefill stage, while the regular HBM-equipped Rubin GPUs handle the memory-bandwidth-bound generation stage.

By contrast, the AMD and Cerebras platform follows the same disaggregation principle, but the specialization is inverted: AMD's Helios platform with Instinct GPUs handles the prefill stage and processes prompts and large context windows, while the Cerebras WSE takes over the decode stage and handles latency-sensitive token generation.

Cerebras plans to install AMD Helios systems in its own data centers and integrate them with its WSE racks. The combined offering is scheduled to become available initially through Cerebras Cloud in the second half of 2026, according to the two companies.

A new semiconductor firm, TYLsemi (pronounced Tile Semi), publicly revealed itself this month, alongside $43 million in early-stage funding and an ambitious plan to simplify the development of custom processors for AI infrastructure.

Dozens of contract chip designers can develop custom processors of different complexity. However, only a few companies can offer custom silicon design services using standard chiplets to speed up and derisk the development cycle. TYLsemi is aiming to join their ranks. We spoke to their founders to find out how the nascent business might pull it off.

Emerging from stealth

Rather than compete solely as another custom ASIC design house, TYLsemi intends to offer reusable, standards-based connectivity, power delivery, and eventually memory chiplets that customers can combine with their own differentiating compute silicon to build a unique system-in-package. For companies that do not intend to conduct semiconductor development themselves, TYLsemi will also provide an end-to-end service that includes design and implementation of a differentiating chiplet, packaging, qualification, and high-volume production, essentially enabling companies without any silicon development skills to offer their own multi-chiplet processors.

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans who have led global engineering, operations, and business teams at Alphawave, SiFive, Cadence, Rambus, and other chip companies, and who collectively have plenty of experience with both standard and custom silicon. Mohit Gupta, a co-founder and chief executive of TYLsemi, believes that the time to establish a company that specializes in pre-approved chiplets and custom ASIC design is right now.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium. "First, advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; there are options from foundries and OSATs, including TSMC, Intel, ASE, and Amkor. Second, die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, which makes heterogeneous integration much more practical. Third, supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure. Those factors have created an environment that did not exist four or five years ago."

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as we have already learned from AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said. "At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

Chiplet economics

The vast majority of AI and HPC accelerators today feature large die sizes, in many cases approaching the size of a reticle. However, as modern process technologies are becoming more complex, foundries tend to increase their quotes for new nodes. A leading-edge wafer used to cost around $15,000 to process around five years ago, but today that price is around $30,000. As a result, large chips at a size close to the reticle limit implemented on a leading-edge node become an option for a select few chip designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects such as UCIe start to make a lot more sense.

"Once dies get into the 500 – 600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices, from $350 million for a monolithic 700 mm² 3nm-class chip to $150 million for a design combining a 500 mm² 3nm-class compute die with four 100 mm² I/O chiplets built on an N-1 process. TYLsemi believes that the unit price of a monolithic chip would be $3,000, whereas the cost of an SiP would be around $600. The company attributes the saving to higher yields, reusable I/O silicon, lower IP licensing and engineering costs, and substantially lower per-unit silicon costs. However, the company stresses that the figures are illustrative estimates rather than actual manufacturing costs. Additionally, multi-chiplet designs can enable faster product refreshes compared to large monolithic dies as they are faster to develop and yield.

"Compute may move to 2nm or A14, while high-speed I/O can remain on 3nm, since I/O does not scale in the same way as logic," Gupta said. "Our power-delivery chiplets can use an even less advanced process. Customers therefore do not have to use the most expensive silicon real estate for every function. […] There is no single answer for every design. You have to determine the right disaggregation points based on the architecture, thermal requirements, package, and how multiple accelerators communicate. […] The exact partitioning will vary by application, but you still get a better total cost of ownership."

TYLsemi primarily targets AI infrastructure, so it generally envisions multi-chiplet designs to be used for AI accelerators, data-center CPUs, high-performance computing, networking and telecom silicon, and heterogeneous SoCs. However, TYLsemi has also ignored the fact that multi-chiplet designs are already widely used for consumer CPUs and GPUs.

Foundation chiplets

At the core of TYLsemi's proposition are its foundation chiplets, which are reusable building blocks intended to handle common non-compute functions in custom AI and infrastructure processors and are implemented using various process technologies from TSMC. The foundation chiplets include the following:

• TYL.IO — a family of connectivity chiplets that includes TYL. IO PCIe, a 32-lane PCIe 7.0/CXL chiplet connected to the compute die via UCIe; TYL.IO Scale, a 224G+ SerDes for ESUN/UALink scale-up connectivity; and TYL.IO EIC for co-packaged optics.
• TYL.Power — a 16nm in-package IVR chiplet with embedded passives, designed to provide power closer to compute dies and use closed-loop control and die telemetry to improve power delivery.
• TYL.Mem — a planned family of memory-connectivity chiplets. TYLsemi has not yet disclosed the architecture or specifications, though it is safe to assume they are talking about memory controllers and PHYs.

Not all of these chiplets will be available immediately, as the company has certain priorities amid limited resources.

"The first TYL.IO product disaggregates the PCIe functionality that would normally sit on a large server processor, it is a 32-lane PCIe Gen7/CXL chiplet connected to the host compute die using UCIe," Gupta explained. "The idea is that the CPU cores can move to 2nm, A14, or another leading-edge process, while the I/O chiplet remains on 3nm. The next product in the family will address scale-up connectivity between XPUs within a rack using high-speed SerDes. That device will be considerably larger, with around 72 lanes and approximately 14 TB/s of bandwidth. We also have an EIC roadmap for co-packaged optical connectivity. We expect samples of our first I/O product in the second half of 2027."

These chiplets can be used as standalone components or integrated with a customer's compute dies designed by the customer to TYLsemi through TYL.Forge, TYLsemi's end-to-end custom silicon platform.

TYL.Forge

TYL.Forge is arguably one of the key enablers of TYLsemi's business, as the program is aimed at companies that have their own compute architecture or even a compute die, but cannot build their own SiP or manage the entire semiconductor supply chain.

"There are larger custom silicon companies in the market, but many of them focus on a relatively small number of customers that can generate billions of dollars in annual business," Gupta explained. "We see an opportunity among emerging AI companies and system companies that need advanced custom silicon but also need a partner capable of taking responsibility for the entire implementation and supply chain."

Such clients can provide their proprietary compute RTL, while TYLsemi handles physical implementation and integrates the resulting compute die with its pre-validated connectivity, power, and eventually memory chiplets. The company then manages tape-out, packaging, assembly, testing, qualification, and high-volume production.

"For example, a customer building a large accelerator can bring us its matrix-multiplication engine," Gupta said. "We can implement the custom compute die and integrate it with our chiplets, so the customer does not have to reinvent the I/O and other common functions. This reduces risk and time to market."

In fact, TYL.Forge appears flexible about where the customer enters the development process. TYLsemi describes the platform as covering everything from architecture and front-end design through implementation, tape-out, assembly, qualification, and production. So instead of RTL, customers can come to TYLsemi with an architecture/concept, and then the company will help develop and implement the silicon. Nonetheless, TYLsemi does not intend to invent the customer's core compute architecture itself. In addition, customers can bring in an existing compute die, which TYLsemi can combine with its chiplets, package, test, and bring to production.

"We are also talking with companies developing Arm- and RISC-V-based server processors," Gupta said. "They can develop the architecture, while we implement the rest of the silicon and bring the product to production. That gives customers an economic and engineering advantage because they do not need to build teams for every part of the chip."

The key advantage of TYL.Forge is the reuse of pre-validated components. Instead of developing common functions such as PCIe connectivity and power delivery for every new processor, customers can use TYLsemi's pre-validated foundation chiplets and focus engineering resources on differentiated compute architectures, software, and system design. In theory, TYLsemi could integrate third-party chiplets (not from a customer, but from a third-party chiplet provider). Still, the company's focus remains on offering its own pre-validated chiplets and custom silicon with SiPs it builds.

"Potentially, [we could integrate third-party UCIe chiplets into a TYLsemi-based system], UCIe has done a very good job defining the electrical interface, but the ecosystem is still maturing at the protocol level," Gupta explained. "In some cases, if we provide a chiplet to a customer, we may also need to provide or enable the UCIe IP on the other side of the connection. We are committed to UCIe and industry standards because standardization ultimately wins. […] We can consider customization for a large strategic customer or hyperscaler, but we do not want those projects to derail our standard product roadmap. […] Even when customers buy our standalone chiplets, I expect many of them will ask us to handle packaging and testing because heterogeneous integration and supply-chain management are difficult "

TYLsemi estimates that its approach can cut development time and cost by up to 50% compared with traditional custom silicon programs. In the best-case scenario, TYLsemi envisions that the development cycle can shrink considerably compared to today's cycles that can be two, three, or more years long. According to TYLsemi, once a customer provides sufficiently mature RTL or a netlist, the company can take a custom compute die to tape-out in around six to nine months or so, which includes fabrication, assembly, testing, and qualification.

"If a customer provides mature final RTL or a netlist and uses our standardized I/O chiplet, we believe we can take the custom compute die to tape-out in approximately six months in some cases," Gupta explained. "More generally, our target is six to nine months from a mature design to tape-out. The architecture and front-end phase is more customer-dependent. For a first-generation product, that can take around six months; for a more mature second- or third-generation design, it could be closer to three months, and some of that work can overlap with implementation. After tape-out, fabrication can take roughly four to five months depending on the process, followed by perhaps another two months for assembly, testing, and qualification. If the architecture is already mature, it may therefore be possible to reach production samples in about a year."

Still, the company stresses that architecture development and implementation typically include feedback loops, which greatly slow the development process. This is why the company provides the relatively conservative '50%' figure.

TYL.IO and TYL.Power samples will be available to qualified customers in 2027, in partnership with TSMC, and the company is looking forward to designing processors for its clients in time for them to reach the market in 2029 – 2030.

Speaking of TSMC, TYLsemi will initially only offer designs and services adhered to the TSMC ecosystem, though eventually it may offer other options for packaging technologies, such as Intel's EMIB and Foveros, or Amkor's packaging methods.

"We are initially focused on the TSMC ecosystem, but we also intend to explore other advanced-packaging supply chains," Gupta said. "We do not want to limit ourselves to one packaging option. Over time, that could include other OSATs and packaging technologies. […] That could include Intel, ASE, Amkor, or others. Amkor, for example, is building significant packaging capacity in Arizona."

AMD's custom Instinct MI450-based AI accelerator for Meta will use three times less memory than the fully-fledged Instinct MI455X and will be optimized primarily for recommendation systems operated by Facebook and other social platforms, according to SemiAnalysis. If the report is accurate, it is reasonable to expect Meta to keep using Nvidia hardware for training frontier AI models and running inference.

The custom Instinct MI455X for Meta will carry 144GB of HBM4 memory using six 8-Hi packages, whereas the full-blown Instinct MI455X will be equipped with 432 GB of HBM4 memory, according to SemiAnalysis. In addition, the part will reportedly offer 'significant decreases in compute.' The new design will offer a more competitive bandwidth-per-dollar ratio for recommendation systems, but will not be optimized for training of frontier AI models or running inference, the report claims.

Cutting compute performance and reducing HBM4 capacity from 432GB to 144GB should dramatically reduce the bill of materials, as HBM4 is exceptionally expensive. Furthermore, the reduction would cut the package size of the custom Instinct MI450-series accelerator for Meta, which is another way to reduce BOM costs. By using custom cut-down Instinct MI450-series accelerators instead of fully-fledged models, Meta can potentially save tens of millions of dollars.

As added bonuses, these custom Instinct MI450-series accelerators will also consume significantly less power when running recommendation workloads without significantly reducing performance. Also, such accelerators can offer better CPU/GPU balance for recommendation systems, according to SemiAnalysis. If Meta runs these accelerators primarily on recommendation workloads for their entire useful lives, the custom design could deliver substantially better total-cost-of-ownership.

However, such cutting down has many disadvantages. The biggest problem is loss of versatility. The reductions in both compute and HBM make it less attractive for LLM training and inference. The standard Instinct MI455X has 432 GB of HBM4 and 19.6 TB/s of bandwidth, which is particularly beneficial for large-scale training and inference. By contrast, the 144 GB capacity may be particularly restrictive for modern LLM training and inference.

In addition, there is also an interchangeability problem. A general-purpose Instinct MI455X can be reassigned from recommendation workloads to training, inference, or other workloads. Meta's specialized version is less attractive outside its intended workload. If Meta's compute demand shifts toward model training and LLM inference, it may find itself sitting on a huge installed base of accelerators optimized for a different workload mix.

As a result, for Meta's model training and inference workloads, the alternative to Meta's cut-down custom MI400 would likely be full-fat AMD Instinct MI455X systems or Nvidia's high-end platforms. Meanwhile, Nvidia has chances to become an obvious beneficiary because Meta already operates massive Nvidia infrastructure. The irony in that Meta customized an AMD accelerator to reduce costs and optimize recommendation systems, but that specialization could force its frontier AI division to buy more general-purpose accelerators — potentially from Nvidia — anyway.

When AMD and Meta inked an agreement under which the former will supply the latter with 6 GW of Instinct AI accelerators over the next five years, they did disclose that at least some of them will be custom accelerators, including custom accelerators based on the Instinct MI450 design. As it seems now, these custom AI accelerators will only be used for select workloads, not a broad set of workloads.

China is considering a major expansion of its technology export restrictions that could cover advanced AI models, training data, and overseas acquisitions of strategically important technology companies, reports the Financial Times. In addition, the Chinese government is mulling over prohibiting local chip designers from making their chips at TSMC and other foreign chipmakers.

The measures would be designed to keep leading-edge AI developments in China as competition with the U.S. in frontier AI and hardware intensifies, but at the same time, they would slow down expansions of Chinese AI standards globally, which generally weakens the country's position.

China's Ministry of Commerce (MofCom) has consulted domestic AI and semiconductor companies about ways to keep critical technologies from transferring abroad or falling under Western control, reports Financial Times citing two people familiar with the talks. Regulators have talked with Alibaba, ByteDance, and Zhipu about potentially limiting transfers of important AI training data outside China and restricting foreign users from downloading model weights.

Overseas customers could still access Chinese AI services and models remotely, so Chinese companies can still monetize their work from foreign customers. However, restrictions on downloadable model weights could still have significant implications for China's AI industry. DeepSeek and Moonshot offer open-weight models that users can download, deploy on their own infrastructure, and modify for specific workloads. Meanwhile, flagship models from Anthropic and OpenAI remain closed, which means that Chinese companies have an edge over rivals that they are about to lose.

In addition, MofCom has reportedly asked for industry feedback on possible restrictions that would prevent overseas chipmakers like TSMC from producing advanced processors based on designs developed by Chinese companies such as Alibaba, ByteDance, and Huawei. This is perhaps the most controversial proposal, as TSMC is clearly ahead of SMIC when it comes to process technology leadership. On the one hand, the move ensures that SMIC will have enough orders to pay for its R&D and expansion. On the other hand, Chinese companies can get better hardware if it is produced by TSMC.

Separately, the Chinese government is considering tighter controls over foreign acquisitions of strategic technology companies, including firms that work on agentic AI technologies. The potential acquisition rules are intended in part to close what Beijing considers a regulatory loophole that enabled Meta to acquire Manus for $2 billion. Chinese authorities subsequently ordered the transaction to be undone.

The measures could be included in the next revision of China's catalogue of technologies prohibited or restricted from export. The catalogue already includes rare-earth materials, their processing technologies, and several lithium-ion battery production technologies.

TSMC intends to raise base quotes on advanced chip production services by up to 10%, according to Nikkei, which cites people with knowledge of the matter. The price hike reflects increased demand for sophisticated processors by the AI sector, raising costs of tools and materials, as well as amplified investments in new production capacities.

For advanced process technologies — which TSMC considers 7nm-class and below — TSMC plans to raise baseline prices by 5% to 10%, depending on the particular production node and customer, the report claims. Furthermore, customers that need additional HPC chip capacity beyond their original volume requirements will reportedly have to pay another 10% to 15% premium on top of the standard increase, which means that some services will get a price hike of around 25%, if the report is accurate.

TSMC also intends to increase prices for mature manufacturing technologies, including its 12nm, 16nm, and 28nm-class nodes as well as other legacy fabrication technologies, the report claims. Increases could reach 10%, although certain nodes will reportedly see smaller adjustments, according to Nikkei.

Advanced technologies generated around 77% of the foundry's revenue in Q2 2026, whereas mature nodes accounted for 23%, which essentially means that TSMC is hiking prices on all of its services.

The company reportedly began discussing the new pricing with customers around June and completed negotiations in July. Rather than introducing higher rates immediately, TSMC opted to implement them from the beginning of 2027 to give clients like Apple, AMD, Nvidia, and MediaTek additional time to accommodate the changes and adjust their prices accordingly.

Since TSMC produces the lion's share of advanced processors for AI, HPC, networking, and smartphone applications, its price hikes will inevitably create a ripple effect in the industry and will make almost all electronics more expensive.

TSMC is not alone in raising prices these days. Vanguard International Semiconductor has also raised prices, while UMC began implementing increases in July. Also, memory makers have increased prices significantly, making TSMC management jealous. Intel also recently increased prices of its client and data center CPUs, citing market demand.

"I am really jealous about memory companies' 86% gross margin," said C.C. Wei, chief executive of TSMC, during the company's earnings call with financial analysts and investors. "86% [margin at memory makers] – 68% [margin at TSMC], I will be happy about that."

TSMC rarely comments on its prices to a large degree because they vary based on volumes and relationship with a particular client. Nonetheless, the head of the company stressed that the company has no intentions to increase prices suddenly or dramatically.

"So we do not suddenly increase our price by which I like to have 4x or 5x," Wei said. "You cannot survive for that kind of... for your customer to survive for that kind of price increase. So we earn our value, and we make sure that our profit, our gross margin, is enough for our long-term sustaining expansion, that is to the benefit of my customers and TSMC also, that is our philosophy."

An analysis of Huawei's Kirin 9030 system-on-chip (SoC) for smartphones conducted by SemiAnalysis revealed that SMIC's third-generation 7nm-class fabrication technology (N+3) has smaller metal pitch than Intel's 18A fabrication technology and that China's leading foundry has managed to achieve transistor density on par with manufacturing process that rely on EUV lithography. But does this make SMIC's N+3 node as competitive as Intel's 18A or TSMC's N2 and N3? Not really.

SemiAnalysis' teardown indicates that SMIC's N+3 fabrication process supports a minimum metal pitch of 32.5nm, which is nominally tighter than the approximately 36nm pitch used for many high-performance cells in Intel's Panther Lake CPU, even though 18A can support approximately 32nm metal pitches. The video from SemiAnalysis and High Yield does not reveal other important characteristics of SMIC's N+3, such as contacted gate pitch (CGP), standard cell height (tracks or nm), or fin pitch, so we cannot make direct comparison of this node to Intel's or TSMC's technologies. What it does reveal is estimated transistor density of around 113.4 million transistors per square millimeter (Mtr/mm²), which is even higher than transistor density of TSMC's N6, 107.7 Mtr/mm².

TSMC's N6 uses multiple EUV layers, so achieving higher transistor density without using EUV lithography is an indisputable technological achievement of SMIC. The foundry achieves this density by using DUV multi-patterning, including self-aligned quadruple patterning on the tightest layers, and extensive design-technology co-optimization (DTCO). In addition, SemiAnalysis believes that SMIC used techniques like reduced fin counts, placing contacts directly over active gates, and tightening cell isolation. Such methods allow for increased transistor density, but at the cost of increased process complexity, cost, yield risks, and design constraints.

Meanwhile, transistor density does not equal overall process competitiveness. Despite its compact layout, the Kirin 9030 reportedly delivers performance comparable to flagship application processors from roughly three years ago and has a substantial energy-efficiency disadvantage compared with modern Apple, Qualcomm, MediaTek, and Samsung designs. Huawei's highest performing CPU core is characterized as roughly Cortex-X2-class in IPC, while Apple's much smaller efficiency cores reportedly outperform it in integer workloads and consume considerably less power.

Given the fact that Kirin 9030 is neither a performance nor efficiency champion, the provocative comparison with Intel 18A is not exactly justified. Although SMIC N+3 has 32.5nm minimum metal pitch that is nominally tighter than the approximately 36nm pitch used in Panther Lake, 18A offers both higher transistor density and considerably higher performance efficiency. In addition, 18A uses gate-all-around transistors and backside power delivery, which make it particularly suitable both for mobile SoCs and for data center applications.

SemiAnalysis concluded that while export restrictions have slowed China's technological progress, progress is still being made. SMIC could potentially continue increasing density by tightening upper and lower metal layers, shorter standard cells, smaller gate pitches, and eventually backside power delivery. If the company continues scaling, N+4 could approach TSMC N5-class density, while N+5 with backside power might reach Intel 18A-class density, according to SemiAnalysis. Still, transistor density alone does not necessarily bring substantial improvements of performance or power efficiency.

ASML is reportedly considering increasing prices of its existing Low-NA EUV lithography tools. The potential price hikes have already upset TSMC, ASML's largest client, reports The Information. But can ASML rapidly raise the prices of the tools it sells to chipmakers? Price adjustments are not going to happen overnight, said Roger Dassen, CFO of ASML, said during the company's quarterly earnings call. But there is one thing to remember about ASML's price hikes: They are going to affect the entire semiconductor industry.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. […] Given the long order lead times that we have, that does not translate into pricing effects tomorrow."

ASML just reported record results for its second quarter of 2026, with total net sales of €9.326 billion ($10.67 billion) and net income of €2.918 billion ($3.338 billion). The company now expects net sales between €43 billion ($49.2 billion) and €45 billion ($51.5 billion) in 2026, a range that comfortably exceeds its own guidance and the expectations of industry analysts.

More complex, more expensive

ASML has generally increased the average selling price of EUV scanners over successive generations as they increase in complexity and productivity, so the idea of higher pricing of EUV tools is not particularly new. The company calls the concept of 'value-based pricing' and gradually increases its average selling price (ASP) based on the value that its tools provide to its operators.

Early ASML Twinscan NXE systems were commonly discussed in the roughly €100 million–€120 million ($115 million-$137 million) range, while later production models such as the NXE:3400C and NXE:3600D moved toward roughly €140 million–€170 million ($160 million-$195 million). The latest NXE:3800E is climbing even further. High-NA EXE systems represent another major step up, at more than €350 million ($400 million) per machine according to industry reports.

Meanwhile, both productivity and performance of ASML's Twinscan NXE systems have been steadily increasing: While the NXE:3400C and NXE:3600D can process 160 – 170 wafers per hour (WPH) and feature a matched machine overlay (MMO) of ≤ 1.1nm, the NXE:3800E and NXE:3800F increase productivity to 220 WPH and 260 WPH, respectively, while increasing MMO to 0.9nm. With the NXE:4200G and NXE:4200H (which will likely feature an all-new light source), we are looking at productivity beyond 300 WPH and MMO of ≤0.8nm - ≤0.7nm.

ASML makes no secret that more advanced EUV lithography tools carry a higher average selling price than their predecessors.

"You should also recognize that the tool mix that we are going to ship next year is a different tool mix from the tool mix that we shipped this year," Dassen said. "When it comes to EUV in particular, the tool mix that we are going to ship next year will be EXE: 3800E and EXE:3800F [tools], while this year it is a combination of EXE:3600D and EXE:3800E [systems]."

ASML's value-based pricing logic is essentially: if an upgraded Low-NA machine processes more wafers and therefore generates more economic value for a fab, ASML can capture part of that additional value through a higher system price. This is what ASML has been doing for some time. That said, the important nuance in Dassen's statement is that he appears to be discussing further price increases for Low-NA EUV tools.

ASML's EUV dominance

ASML is the only supplier of EUV lithography systems on the planet; every single chipmaker must comeq to the company to get one of these scanners, so the company sells these machines years in advance. This year, the company expects to have the capacity to build 65 EUV tools and intends to increase capacity by 30% next year to around 84 – 85 EUV systems. In 2028, ASML plans to produce 110 EUV scanners.

"For 2027, we are now close to being fully covered with orders for Low-NA EUV, and we are planning to increase our Low-NA EUV capacity by around 30%," Dassen said. "Looking ahead to 2028, we have already received a significant number of Low-NA EUV orders. Strong demand forecasts from our customers have led us to investigate a further 30% capacity increase for that year."

Given the strong demand for ASML's tools, the company is in a position to increase prices, at least according to the rules of the free market. As always, comments on pricing are made in opaque corporate language, so one can make a lot out of it, or nothing at all.

"Clearly, the environment that we live in today, with the [substantial] value that our products bring to customer, of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, it is not that easy for ASML to just hike prices overnight, and there are important things to note. When ASML gets an order, and that order enters the reported backlog (which totaled €38.8 billion as of late Q4 2025), it already carries a sales value (with a possibility of inflation adjustments), so there is necessarily an agreed or otherwise contractually determined price basis attached to it.

This makes Dassen's comments particularly interesting. If ASML is already close to fully booked for 2027 Low-NA EUV capacity and has received a significant number of Low-NA orders for 2028, then much of that capacity is already represented by customer orders with associated sales values. As a result, unless ASML can subsequently renegotiate the fixed price before delivery, it cannot hike prices on tools that it intends to ship in 2027 and part of 2028. This essentially means that ASML could only book new orders that it intends to ship in 2028 (presumably for the second half of the year) and onwards at higher prices. However, ASML has not confirmed this directly.

ASML's next-generation NXE:4200G is on track to arrive in 2029. That scanner is poised to be more expensive than the NXE:3800E/NXE:3800F anyway, so the company's Low-NA EUV ASPs will inevitably get a bump that year. Of course, ASML is set to continue shipping its EXE:3800-series after 2029. The big question is whether the company will adjust the prices of these units that will ship starting in 2028 or not.

We do not know the answer to this question, unfortunately. But during the conference call, ASML's financial chief implied that the company would like to get 'rewards' from its customers not only for improved productivity, but also for other improvements of its tools, which means that ASML will stick to its value-based pricing model, but may adjust the pricing for the EXE:3800 model.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. [But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out, which, put in another way, customers were paying for the productivity upgrade, and the value that we gave them for free was the value associated with, let us say, overlay improvement, imaging quality […]. In the current environment, with the value that we bring, we are also having conversations with customers on how we get rewarded for that additional value."

TSMC's backlash against the price hikes

As ASML will likely not be able to hike prices on EUV tools that have already been pre-ordered and which are set to be delivered in the course of the next two years, existing chipmakers like TSMC will not feel the effects of the price increase at least over the next 24 months. Of course, if ASML adjusts prices of its EXE:3800-series scanners due to ship in 2028 – 2028, nobody is going to be happy. And yet, TSMC seems to be so upset that the sentiment has made it to the press. There are several reasons behind the reported backlash, but the major one seems to be strategic.

For years, TSMC has said that ASML's High-NA EUV lithography tools were too expensive, and that the company's engineers can continue innovating using Low-NA EUV systems. Also, adopting all-new High-NA EUV scanners will not be an easy undertaking in general, as the transition also requires new photoresists, photomasks, pellicles, metrology equipment, design rules, computational lithography flows, and numerous other supporting technologies and process innovations.

TSMC's mid-term expansion strategy, as well as a leading-edge roadmap through 2030, has been built around extracting more performance and resolution from conventional Low-NA EUV scanners using techniques such as improved masks, computational lithography, and multi-patterning where necessary. If ASML proceeds with its price hikes for Low-NA EUV tools, this can seriously hit one of the key economic foundations of TSMC's strategy.

TSMC's intention to avoid the usage of High-NA EUV scanners until at least 10A-class (1nm) process technology has an important economic advantage. A High-NA EUV system costs more than €350 million, whereas Low-NA systems are substantially cheaper. As a result, TSMC can choose its own trade-off between additional process steps and buying much more expensive lithography equipment. In contrast, Intel, which is set to adopt High-NA EUV lithography for its 14A fabrication process, has much less flexibility: If a particular process technology is designed around High-NA EUV layers, these extremely expensive scanners, along with other ingredients, become part of the manufacturing flow and affect wafer pricing.

One of the reasons TSMC would like to extend usage of Low-NA EUV systems is that it already has the world's largest install base of these tools, as well as mature processes, established flows, and plenty of innovations that enable it to stay ahead of the competition. However, if ASML systematically ties productivity improvements of each new Low-NA EUV generation to higher prices, the cost advantage of staying with Low-NA EUV gradually narrows, which greatly undermines TSMC's strategy.

There are several other reasons for TSMC to be particularly unhappy with ASML. Firstly, TSMC needs an enormous number of tools for its upcoming fabs in Taiwan, the U.S., and Japan. All of the company's leading-edge process technologies through 2029 rely on Low-NA EUV production tools. Even a relatively modest percentage increase applied to dozens of Low-NA EUV scanners can add billions of dollars to the company's capital expenditure (CapEx).

Secondly, ASML is essentially arguing that it deserves a share of its customers' improved economics. From TSMC's perspective, potential price adjustments are very different from charging more because a new scanner is materially more expensive to manufacture. ASML is effectively saying: 'Your fabs are more profitable, and our tools are more productive, therefore we want a piece of that.'

Thirdly, pricing negotiated today determines pricing and TSMC's economy for years to come. Now that ASML is sold out for 2027 and a significant part of 2028, it is negotiating terms for the second half of 2028 and onwards. Accepting a substantial increase now will inevitably carry through to dozens or hundreds of future Low-NA EUV systems, which directly affects TSMC's economics.

TSMC's A14 (1.4nm-class) fabrication process has made rapid progress in the last three months and is well ahead of N2 at the same stage of development, according to the company's update provided at its earnings call this week. The technology also faces strong customer interest and engagement across both smartphone and AI/HPC applications.

"A14 technology development is on track and progressing well. Internal product-like vehicle demonstrated close to 90% device performance and close to 90% 256Mb SRAM yield," said C.C. Wei, chief executive of TSMC, during the earnings call with analysts and investors.

A14 — which is expected to enter mass production in 2H 2028 — is making rapid progress in terms of performance and yield improvements. This April, the company disclosed that the production node achieved >85% target transistor performance and >80% 256Mb SRAM yield. Roughly three months later, both figures are approaching 90%, which suggests a gain of around 5% in device performance and nearly 10% in SRAM yield.

For comparison, TSMC's N2 demonstrated more than 80% of its target device performance and over 50% yield on a 256Mb SRAM test chip in April 2023. By April 2024, the process had advanced to more than 90% of its target device performance and over 80% SRAM yield. While development trajectories are not directly comparable, the figures suggest that A14 is maturing considerably faster than N2 did at a similar stage of development.

The very rapid progress of A14 compared to the relatively slow maturation of N2 at similar stages of development can probably be attributed, at least in part, to TSMC's growing experience with gate-all-around (GAA) nanosheet transistors. Back in 2023, the company barely had enough experience with the production of gate-all-around (GAA) nanosheet transistors, as N2 is its first process technology to adopt such a structure. By contrast, A14 relies on TSMC's 2nd Generation of GAA devices, so it can probably benefit from the transistor-design improvements, process refinements, and manufacturing expertise accumulated during the development and ramp of N2.

It appears TSMC has likely eliminated many of the yield limiters with A14 and N2, though keep in mind that a high 256Mb SRAM yield merely indicates low enough defect density and good process uniformity across a highly repetitive test structure, but it is not directly representative of functional or parametric yield of a commercial processor.

Nonetheless, the close to 90% device performance and close to 90% 256Mb SRAM yield about 2.5 years away from expected mass production start put TSMC's A14 progress well ahead of N2. Such progress can potentially enable TSMC to start high-volume manufacturing (HVM) using A14 ahead of schedule, provided that customer designs are ready, or initiate HVM with better-than-usual functional and parametric yields.

Speaking of customer design readiness, Wei indicated that clients strive to tape-out their A14 designs ahead of schedule, which is a good sign. It is also interesting to note that despite the fact that A14 lacks Super Power Rail backside power delivery (A12 will gain SPR in 2H 2019), it is set to be adopted not only by client processors, but also by AI/HPC applications.

"We are observing a strong level of customer interest and engagement on both smartphone and HPC/AI applications, and customer new tap-out activity is ongoing and ahead of schedule," Wei said.

A14 is TSMC's next-generation process technology that combines the company's 2nd Generation GAA nanosheet transistors with a new standard-cell architecture to improve performance, power efficiency, and transistor density. Compared with N2, TSMC expects A14 to deliver a 10% – 15% performance uplift at the same power and transistor count, or reduce power consumption by 25%–30% at the same frequency and complexity. The node is also projected to increase transistor density by around 20% for mixed designs and by 23% for logic.

As Apple and other American companies seek to use memory chips from China-based CXMT and YMTC amid massive supply constraints, U.S. lawmakers want to ban exports of Chinese memory chips to the U.S., citing concerns of weakening domestic and allied suppliers and indirectly supporting the development of 3D NAND and DRAM by Chinese companies, reports the Financial Times.

John Moolenaar, Republican chair of the U.S. House China Committee, and Democratic Congressman George Whitesides asked Commerce Secretary Howard Lutnick to prevent U.S. companies from purchasing semiconductors from businesses included either on the Pentagon's Chinese Military Companies blacklist or the Commerce Department's Entity List. They also called on the administration to add CXMT to the Entity List and impose additional restrictions on YMTC.

"Dependence on Chinese memory manufacturers creates an unacceptable risk for U.S. national security, economic security, and supply chain security," the letter by Moolenaar and Whitesides reads.

Apple has been seeking approval from the Trump administration to source memory from CXMT amid a severe global DRAM supply crisis caused by the rapid expansion of AI infrastructure. Corsair, Patriot Memory, and some other suppliers of branded memory modules and SSDs have been using DRAM from CXMT and 3D NAND from Yangtze Memory for some time now.

"We are alarmed that Apple and other U.S. tech companies seek to purchase memory from Chinese semiconductor manufacturers, including those with ties to the Chinese military," the U.S. lawmakers wrote.

DRAM maker CXMT is already on the Pentagon's Chinese Military Companies list, whereas 3D NAND producer YMTC is already in the DoC's Entity List. Their presence in the lists does not outright prevent American companies like Apple from buying their products, but at a significant political risk.

Technically, American companies could buy chips from CXMT and YMTC to use inside products bound for China or other countries and continue to use memory from traditional suppliers in products aimed at the U.S. market. To prevent this, Moolenaar and Whitesides also urge the American government to coordinate with Japan, South Korea, and the EU to prevent CXMT and YMTC from taking advantage of the current supply shortage to establish themselves in allied supply chains, which they believe could ultimately leave the West strategically dependent on Chinese memory.

Moolenaar and Whitesides argue that purchases from Chinese memory manufacturers could indirectly support technologies applicable to China's military.

"Leading Chinese memory manufacturers are all closely intertwined with the Chinese military; thus, every memory purchase by a U.S. company will directly subsidize the People’s Liberation Army's development of this critical dual-use technology," the letter stresses.

The lawmakers argue that CXMT and YMTC could repeat China’s playbook in solar, steel, telecom, and EV markets: use state subsidies to undercut foreign rivals, weaken their investments, and ultimately exploit the resulting dependence for strategic leverage. That said, using Chinese memory now could permanently weaken Western production capacity and leave the West strategically dependent on China for a critical component of AI infrastructure, Moolenaar and Whitesides believe.

As the semiconductor industry increasingly relies on ASML's EUV lithography tools both for logic and memory production, ASML is considering increasing prices of these systems as they deliver greater productivity and better value for its customers. However, with 2027 production nearly sold out and substantial 2028 orders already booked, meaningful increases may primarily affect systems delivered from late 2028 onward. Nonetheless, the idea has already angered TSMC, ASML's largest client, reports The Information.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. "Given the long order lead times that we have, that... doesn't translate into pricing effects tomorrow."

Value-based pricing set to persist… in a new way

ASML has long followed what it calls value-based pricing and gradually increased its quotes based on output, patterning costs, power consumption, and other benefits its new tools offer to clients.

Usually, this involved increasing prices once in a while. For example, if early Twinscan NXE Low-NA EUV systems cost roughly €100 million – €120 million ($115 million–$137 million), the more advanced are priced starting at €170 million ($195 million. It is still well below rumored quotes for High-NA EXE scanners that exceed €350 million ($400 million). At the same time, Low-NA productivity has risen from 160–170 wafers per hour (WPH) and ≤1.1nm matched-machine overlay to 220 WPH/260 WPH with NXE:3800E/NXE:3800F at 0.9nm. Future NXE:4200G/NXE:4200H systems are expected to exceed 300 WPH and improve overlay to ≤0.8nm–≤0.7nm.

"Clearly, the environment that we live in today, with the value that our products bring to customer — it's substantial— of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, later during the call, Dassen emphasized that ASML intends to maintain its value-based approach even in the current environment of high demand and limited supply in the semiconductor world. Yet, he stressed that from now on, ASML might want to charge for things beyond just productivity.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. "[But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out," he said, suggesting that ASML shares value with its clients.

No price hikes in the short term

ASML will be unable to hike prices of Low-NA EUV systems for another couple of years. Since orders that are in ASML's backlog already carry a sales value, subject to inflation adjustments, prices for much of the 2027 and early 2028 output may already be contractually determined. Unless existing contracts can be renegotiated, higher pricing could therefore primarily apply to 2028 shipments and beyond, or for new orders that somehow get squeezed in in 2027. The NXE:4200G, due in 2029, should naturally lift average selling prices anyway as it gets major performance improvements.

TSMC is upset

For TSMC, however, the issue is strategic. The foundry's leading-edge roadmap through 2030 relies on extending Low-NA EUV with better masks, computational lithography, and multipatterning. Until then, TSMC's strategy has always been avoiding High-NA EUV until at least its 10A-class (1 nm-class) technology. If ASML hikes prices of its future Low-NA EUV lithography systems, it will likely affect all of TSMC's plans for the next several years.

TSMC already operates the world's largest Low-NA EUV fleet and needs many more scanners for fabs in Taiwan, the U.S., and Japan as it executes its global expansion strategy. Consequently, even modest increases beyond TSMC's projections could add billions to capital spending, reduce the economic advantage of postponing High-NA, and ultimately raise its manufacturing costs. Moreover, accepting higher prices now could establish the baseline for dozens or hundreds of future systems, which will allow ASML to capture a larger share of the economic value created by increasingly productive lithography equipment.

Can this force TSMC to transition to High-NA EUV tools earlier than planned? Moving to High-NA EUV requires not only €350-million-plus scanners but also new resists, masks, pellicles, metrology, design rules, and computational lithography flows, which are likely not ready at TSMC.

Jensen Huang, chief executive of Nvidia, denied reports about delays of the company's next-generation AI platform and said that production volumes of the upcoming Vera Rubin platforms are 'giant.' He didn't address reports about delays of Vera Rubin Ultra-based rack-scale systems carrying 144 AI GPUs.

"[The reports about Vera Rubin delays are] not true," Huang told reporters on the sidelines of an event in Japan, reports Bloomberg. "Vera Rubin is already in production. Giant amounts of production incoming."

Nvidia confirmed production of its Vera Rubin platform in January and then sampling in February, so the current comment reiterates what we already know. Nvidia stressing that 'giant amounts of production' are incoming is meant to reassure investors that the company is on track to sell a boatload of its next-generation Vera CPUs, Rubin GPUs, and Vera Rubin NVL72 systems in the coming quarters, which means more record-setting quarters.

What Huang did not address — or perhaps he wasn't asked — is Nvidia's rumored delay of its Kyber NVL144 rack-scale solution with copper interconnects due to the system's complex PCB midplane by more than a year from 2027 to 2028. An alternative dual-rack design has reportedly been canceled and an even larger CPO-based NVL576 configuration may also face delays or limited availability, the same report from SemiAnalysis claimed earlier this month. The setback could leave Nvidia's Rubin Ultra platform with a smaller NVLink scale-up domain than originally envisioned. Nvidia says its roadmap is intact.

The Kyber NVL144 architecture was designed to connect 144 Rubin Ultra GPUs using a copper-based NVLink 7 scale-up fabric, so the machine required a sophisticated PCB midplane to carry high-speed electrical links between the system's components. SemiAnalysis claims that this midplane was challenging to manufacture, leading to a delay. The report does not identify defective chips or problems with particular components mounted on the board, but specifically points to the manufacturability of the PCB infrastructure itself.

"Our roadmap is intact," a spokesperson for Nvidia told Tom's Hardware.

Nvidia's statement on the matter neither confirms nor denies the report, but indicates that the company will be able to offer products mentioned in its roadmap without revealing whether they also remain on their previously announced launch schedules.

Nvidia reportedly considered another copper-based design, called NVL72x2, as an alternative to Kyber. The system would have placed two Oberon racks back-to-back to expand the size of the NVLink scale-up domain without using optical interconnects. However, SemiAnalysis says customers rejected the unusual design and operational requirements, but does not specify their individual objections that could include serviceability, cooling, cabling, and data-center layout.

Meanwhile, the planned NVL576 rack scale solution that was supposed to combine eight Oberon racks interconnected using co-packaged optics between NVSwitches has also been postponed, or shipped in relatively small quantities because of 'ongoing CPO challenges,' SemiAnalysis claims.

The existence of the planned NVL576 configuration suggests that Nvidia had been developing some form of CPO-enabled NVSwitch connectivity for the Rubin generation. In theory, similar optical switch-to-switch connectivity could potentially be used to join smaller GPU groups into an NVL144 system and bypass Kyber's problematic copper midplane. However, the available information does not clearly indicate whether the CPO technology intended for NVL576 could reproduce Kyber's topology, bandwidth, and latency characteristics, or whether it was sufficiently mature for high-volume deployments by potential NVL144 customers.

The reported Kyber delay comes on the heels of another report saying that Nvidia had canceled quad-compute-chiplet version of its Rubin Ultra in favor or a dual-compute-chiplet design that is projected to deliver 2X lower performance. With Kyber NVL144 delayed and NVL72x2 cancelled, Nvidia will only be able to offer 72-way scale-up systems till sometimes in 2028, meaning that AMD and Google may end up with more competitive scale-up systems in 2027 – 2028. AMD's Mega Pod based on the Verano CPUs and Instinct MI500-series accelerators, is expected to pack up to 256 accelerators. Google's TPU 8i can provide roughly 1,024–1,152 accelerators within one low-latency domain, whereas the TPU 8t goes much further and can get to 9,600 chip packages per domain.