Cadence, one of the largest electronic design automation (EDA) companies, has unveiled Maestro, its new portfolio of domain-specialized AI models tailored for its chip design agents, in a press release sent just ahead of earnings. In initial results compared with general-purpose AI models, Cadence claims up to a 30% improvement in the quality of results and that Maestro effectively uses fewer tokens for the same task, with up to 5x the token efficiency. The first models “are available to select early access customers” in Q4 2026, and customers may run them on Cadence’s cloud, public clouds, or customer-controlled on-premises environments and post-train them on their own “proprietary data, designs, and workflows.” To learn more about Maestro, we spoke with two Cadence executives: Rob Knoth, senior group director of strategy and new ventures, and Paul Cunningham, senior vice president and general manager.

This approach is distinct from Synopsys’ own specialized model, GPT-Synopsys, which will run on OpenAI-hosted infrastructure, without using customer data to train the model. The models of both EDA giants, announced less than a month apart, now split on where a customer’s design data goes. Where they might not differ is why: Paul Cunningham, senior vice president and general manager at Cadence, told Tom’s Hardware Premium that agent costs have “really started to explode,” adding, “And I think the world realized so.” That makes it a natural step, he said, to move more of the agents’ iterating “into the weights of the models themselves.”

Maestro takes this step through Cadence’s AI Super Agents, which “interpret design intent, decompose tasks” and “orchestrate the Maestro portfolio with other leading frontier and open-weight models,” evaluating trade-offs to guide decisions with domain expertise. It also uses reinforcement learning (RL), where Cadence’s “deterministic solvers evaluate outputs against engineering objectives, constraints and ground truth,” and, importantly, the results feed back into the models for improvement.

The models include Nvidia’s Nemotron, and customers can run the customer-data training step themselves with Cadence’s fine-tuning harness, potentially “on their own GPUs, on their own network,” Cunningham said. He added that Nemotron, specifically, was “giving really solid results and actually improving very, very fast.”

One constant that keeps popping up with agentic EDA is the need to nail down what the numbers actually measure. In chip design, quality of results usually refers to the design’s power, performance, and area, though Cadence didn’t specify what its 30% figure measures. Both it and the 5x token efficiency figure are measured against “a general-purpose foundation model,” which Cadence told us is the open-source model Maestro started from before its training. The company wouldn’t name the foundational AI model that Maestro is derived from beyond mentioning that it is “one of the leading open source models that’s very competitive with commercial frontier models.”

Cadence credits the token savings to balancing its EDA and system design automation (SDA) “tool calls with LLM invocations.” As an analogy, Cunningham said, “You don’t need to drive to Safeway in the jet engine,” and you want to use “the right model at the right time for the right task.”

Runtime does matter, too: as Rob Knoth, senior group director of strategy and new ventures at Cadence, told Tom’s Hardware Premium in September that a tool call could take anywhere from hours to days to return a value, while the AI industry’s training loops are “used to minutes.” Efficiency could also lower costs, since Maestro use counts toward Cadence’s agent pricing, a subscription with a consumption allowance and charges for use beyond it, Cunningham said. He didn’t say whether the token savings cut a customer’s bill.

Being flexible for the customer is a key element of any solution, and for Cadence’s competitor Synopsys, this lies in Autopilot, which Synopsys says allows customers to “choose among commercial, open-source, and fine-tuned language models” across “Synopsys-managed and customer-managed deployments,” with cloud or on-premises infrastructure. For agent security, such as sandboxing, Cadence says it’s working with Nvidia on an integration with Nvidia’s OpenShell Reference Architecture, which Nvidia launched last week, naming both Cadence and Synopsys. These options can help protect customer intellectual property.

Cadence has had a busy 12 months with customers and agents alike. During Cadence’s July earnings call, CEO Anirudh Devgan said ChipStack, its design and verification agent, “has more than 20 customer engagements,” and ViraStack, its custom and analog agent, “more than 25 customer engagements.” Socionext said just last week that it was applying InnoStack. Silicon Labs has also credited ChipStack with accelerating debugging, and both companies say they are watching Maestro next.

Cadence's agentic consolidation began with its acquisition of ChipStack back in November 2025. In June 2026, the company claimed that its agent had reached Level 5 autonomy, which we explored in detail. In September, Knoth teased Maestro’s ingredients to Tom's Hardware Premium a month early, two days before the GPT-Synopsys announcement: “reinforcement learning loops, domain-specific post-training of open-weight models, model routing.” Maestro is now sitting under all four super agents, targeting a similar year-end window to Synopsys’ Autopilot; the table below has the full timeline.

This rapid pace of progress means that a clear distinction has to be made between early access and general availability. Both Cadence and Synopsys can point to customer engagements, and, at least in the latter’s case for the AgentEngineer portfolio and Autopilot platform, general availability remains a goal by year’s end; Cadence hasn’t given a general availability date for Maestro. For GPT-Synopsys, though, only “early technology engagements are underway,” according to its partners. The platforms and agents remain works in progress.

For Maestro, Cunningham hopes for “more case studies, more quantifiable benefits” through Q4. The real story, as he aptly put it, is that “we’re going to bring agents and agentic AI natively into our vertical, not that our vertical is going to get embedded into general-purpose agents.” Only customer results on real workflows will test Cadence’s 30% number, but going by what both companies have shown so far, their own early figures are extremely promising and exciting for the EDA industry.

Modders have discovered a way to remove imposed half-speed AI performance limits on Nvidia RTX 20, 30, and 40-series GPUs with a firmware exploit, VideoCardz reports. Without the limitation, the RTX 4090 can achieve double its peak tensor rate, and matrix math can improve by up to 80% for the RTX 3090 Ti, with gains on other cards varying. Real workloads gain significantly less than the RTX 4090’s doubled peak would imply, and chatbot token speeds remain about the same, as that performance is dependent on memory bandwidth.

For all impacted GeForce generations, Nvidia imposed a limit that, per its own published specs, runs FP32-accumulate math at half each card’s FP16-accumulate rate. That does not apply to its Turing and Ampere pro cards. The unlock returns native matrix-math throughput to owners of the cards, which can speed up prompt processing and image generation.

Three separate projects offer generation unlocks, each with its own unofficial Linux module, while experimental Windows builds pursue a different approach. Card coverage varies by generation, with gpu-unlock handling Ampere and listing the GA102/GA103/GA104/GA106 series IDs. An Ada fork, gpu-unlock-ada, covers the RTX 4090 and, experimentally, the 4090 D, 4070 Ti Super, and the 4060 Ti 16GB. The turing-unlock project, adapted from gpu-unlock, works with the RTX 2080 Ti. See Table 1 for a breakdown.

How much faster the cards get

The peak doubling is for tensor rates, with the Ada fork developer’s RTX 4090 moving from 165.6 to 331.6 TFLOPS on FP16 and 165.5 to 330.6 TFLOPS on BF16. The gpu-unlock-ada README states that, in one independent owner’s matrix-multiply benchmark, cuBLAS GEMM medians only saw improvements of 12–34% and up to 20%, respectively. A separate data point, for an RTX 4070 Ti on Windows, saw larger matrix-multiply gains of +80.1% and +76.4%, the difference possibly caused by power limits.

In the matrix-multiply benchmark, a tested RTX 3090 Ti scored +35% for FP16, +80% for BF16, and +94% for TF32, based on a user’s test with a modified Nvidia driver. The gpu-unlock README lists BF16 matrix-multiply gains from user reports of +25–67% for the RTX 3090, +70–73% for the 3080 10GB, +56–59% for a memory-modded 20GB version, +73–81% for the 3070, and around +80% for the 3060 12GB, though it notes they are not directly comparable. The power limit “matters a lot”: the lowest figure, +25%, came from cards capped at 225 W. For Ampere, LLM prefill improved 14–36%, with diffusion and FlashAttention speeding up, but LLM decode and INT8 stayed “about the same.”

An RTX 2080 Ti with a 22GB memory mod, a Dell OEM card limited to 250 W, saw FP16 matrix-multiply improvements of +36% to +64% depending on size; BF16 is unaffected, since Turing has no BF16 hardware. A user’s variant of the card at 260 W saw a +59% improvement. A separate project, KohakUnlock, on a Leadtek 2080 Ti 22GB saw an 85% improvement on an instruction rate test, with a best matrix-multiply median of +53% against a second, locked card of the same model.

There is “not a claim of a 2× application/game speedup,” says KohakUnlock’s README. See Table 2 for a rundown of the numbers for all three generations. The turing-unlock README notes that the mod “may damage your hardware,” while KohakUnlock adds that it “can hang a GPU or host, prevent boot, corrupt data, or damage hardware,” so caution is advised.

How the exploit works

The explainer for gpu-unlock states that the rate limits are in two “speed selector” registers that the host driver can’t write, but Nvidia’s signed SEC2 “Booter” firmware has a stack buffer overflow which can be exploited to run code in “heavy secure” mode. This was discovered after Nvidia published a debug Booter encrypted with a known public test key. A single 4-byte write with the V67 payload opens the privilege mask so the host can set the full rate, and the module then resets the card before Nvidia’s driver binds it.

The underlying bug is described in Jon Pry’s “A Canary in the Crypto Mine: Defeating Stack Protection in a GPU Secure Coprocessor,” published on Zenodo in June. The stack overflow was found on the CMP 170HX in the Heavy Secure Falcon, and the V67 constants come from WildFlash1st/cmp90hx-unlock. The pre-driver timing gpu-unlock uses appear to come from WildFlash1st’s separate Windows EFI bootloader, cmp90hx-unlock-for-windows, while the best-known use of the exploit is the CMP Unlocker for the CMP 170HX. Zagitta, the maintainer of gpu-unlock, said on Hacker News that the project is their work but “the exploits … aren’t my ideas by any means” and that the unlock “just flips the 2 bits” needed.

Zagitta said that RTX 40 support is in progress and that forks are already unlocking those cards. Zagitta added that Hopper and Blackwell cards are “out of scope for this approach” at least.

The Ada fork says other boards “remain unverified” and that shared firmware “does not establish support for untested cards.” The turing-unlock project, likewise, has a list of untested Turing IDs. Gaps remain for GA103 and most Ada and Turing cards. None of the projects contains a roadmap, but data is being gathered, as gpu-unlock is asking GPU owners for compatibility reports.

OpenAI’s AI agents built hidden channels to talk across walls put up between them in red-team tests, communicating by manipulating the CPU cache with no network link or shared file, according to a company blog post. The containment was intended to stop that kind of secret-swapping, but the agents found multiple ways around it when asked. Security researchers already showed that a covert cache channel can move data between cloud virtual machines (VMs); a hijacked agent on a shared cloud server could, in theory, exchange data on the same physical machine, and do so undetected by network monitoring.

The agents in question were set up in separate microVMs, on shared hosts, with OpenAI’s sandboxing software, and were asked to swap synthetic secrets without a network connection or shared writable files. One agent evicted select data from the CPU’s cache while another timed the reloading, enabling the two to communicate with fast and slow reads using a protocol they agreed on first. The same cache-timing technique was used to extract data in the Spectre and Meltdown attacks; but unlike in those cases, the covert channel here needs two willing parties.

One X user, tech commentator Ryan Orhan, wrote that the isolation “wasn’t necessarily broken at the software level,” calling it “a pretty remarkable demonstration of why secure agent containment is such a difficult problem.”

The company’s concern is that models might “find unauthorized ways to communicate with agents in other sandboxes,” with communication outside permitted channels constituting a failure of containment. A 2017 paper at the NDSS security conference demonstrated a covert cache channel between two Amazon EC2 VMs, fast enough to carry an SSH connection, but now agents can build one themselves when asked, including the encoding process. In principle, such a channel could be weaponized, with the sender being code an attacker controls or directs, for example, a prompt-injected agent in a cloud sandbox. The receiver could be a process on the same physical machine, and the data would then leave without any network traffic for monitoring to catch.

The agents turned up three other channels, too: shared storage, where one agent alternated bursts of writes with idle time while the other timed the difference; competition for CPU time in a shared execution container; and a TLS certificate cache in OpenAI’s offline web setup. In most of these tests, OpenAI pointed the agents at the channel or gave them a protocol, and most of the channels are slow and hard for models to exploit.

The red-team testing involved teams of frontier-model agents that worked in parallel and cooperatively toward three objectives: to reach the live internet, to cross an internal security boundary, and to talk across isolation boundaries. Extra tests assumed the inner protections had already failed, with an agent out of its sandbox, past the monitors and in full control of its host machine, to see whether it could still reach the live internet.

The agents came from some of the company’s most capable models, including the “upcoming GPT-6 Astra Cyber model and an internal frontier model,” and were given infrastructure source code, configuration details, and documentation describing potential vulnerabilities, so the defenses were tested under conditions favorable to an attacker. The tests ran on isolated, purpose-built copies of the company’s research infrastructure and used “hundreds of billions of tokens” in total.

The post comes after several cybersecurity incidents involving OpenAI’s agents, including the July Hugging Face breach and a Sept. 20 DNS episode that led to an 11-day pause in training. With training resumed Oct. 1, the company continues to disclose vulnerabilities across “several microVM projects” and has made red-teaming with its most capable models part of the safety cases that decide whether training and evaluation go ahead. The company believes future models will be able to find vulnerabilities not yet known about.

China-state-aligned actor Storm-0940 used ARTEX, an open-source agentic AI penetration testing framework, in its large-scale ConnectWise supply chain attack, Microsoft wrote in its Security blog. After unauthorized access to the multi-tenant application, the group attempted sign-ins at more than 2,250 Microsoft 365 tenants, with stolen ConnectWise app credentials that authenticated as the apps with no interactive user sign-in. Some of the group’s attacks reached privileged access less than three hours after initial targeting.

Automated password guessing, or password spraying, also targeted 327 accounts across eight organizations with more than 151,000 failed logons and no successes. The use of ARTEX, “a system of LLM-driven agents that run an autonomous penetration test,” sped up scanning and reconnaissance, password spraying, and OAuth application abuse. The agents can work around the clock “with little needed human interaction,” at a pace that “leaves defenders with little time to detect and respond.” It’s uncertain how the ConnectWise credentials were stolen or how many tenants were actually compromised.

Storm-0940, active since 2021, is a “China-state aligned actor” with “no known industry aliases,” and its name follows the convention for a developing actor. Industries targeted this time include aerospace and defense, semiconductor, government, and think tanks, with 14 listed in total. The activity “did not result from a compromise of or a vulnerability” in Microsoft’s systems, products, or services.

At its peak on Oct. 11, the password spray engaged in 2,900 attempts, all failures, per minute, at more than 111,000 for that day, with 48 accounts logging more than 1,000 failures each. Almost 98% of this activity was locked out. However, with control of the identities of multiple ConnectWise cloud apps, the attacking AI agents signed in to customer tenants from the same IP range using those apps’ credentials, with more than 200 sign-ins in under four minutes using four application credentials. Operations taken within some tenants include Graph and directory operations, reconnaissance, app credential changes, plus changes to identities, groups, and privileged roles.

In one tenant on Oct. 15, Huntress, a security firm, saw an app add itself to the top administrator role, the behavior behind the Microsoft Defender alert “Application self-assigned Global Administrator role.” Actions included planting new secrets set to expire in 2028. It confirmed unauthorized sign-ins for 162 tenants by Oct. 16 and, a day later, almost 1,000 Entra tenants with sign-in activity from the attacking IP, with more than 300 succeeding. The attack’s sweep through tenants in sorted order, a few seconds apart, indicated “a script working from a target list.”

What differs from many traditional attacks is the use of the open-source pentest framework that, Microsoft says, can use any AI model. Threat actors in multiple regions are using the technology, and public reporting this month tied it to breaches at South Korean financial institutions. CrowdStrike said the suspect in those separate attacks was likely based in China and allegedly used ARTEX with Anthropic’s Claude Code. ARTEX’s developer, who goes by the handle “Autumn-27,” said on GitHub that the ARTEX project “will no longer be updated” and would become closed source, Reuters reported.

ConnectWise noted the unauthorized access and suspended Cloud Backup (formerly SkyKick) as well as SaaS Security and Cloud Management as a precaution. It has started a phased restoration with recovery expected to take several days and has no indicators to date that partner backup data was compromised. Microsoft notes that an affected app, or even a successful sign-in, doesn’t necessarily mean data was accessed or taken, and advises customers to keep affected app connections disabled until formal restoration instructions are issued, and to review activity from this month where logs allow.

Electronic Arts (EA) is closing BioWare and its Edmonton studio, according to a recent letter to employees, which confirms that early development on the next Mass Effect game has also been canceled. The studio was behind Mass Effect and other popular franchises such as Dragon Age, Star Wars: Knights of the Old Republic, Neverwinter Nights, and Baldur’s Gate during its 31-year history. EA is focusing on Battlefield, Iron Man, and a Fight Night revival instead.

BioWare, a “legendary studio,” in EA’s words, had a small team working on early development of the next Mass Effect game, but the company “made the decision not to move forward with this development.” BioWare was acquired by EA in 2008, and EA itself went private in August. The next game in the series was first announced in November 2020 and teased that December with an official trailer on EA’s Mass Effect YouTube channel. In 2021, the Mass Effect Legendary Edition remaster of the original trilogy was released. Since then, the studio has been relatively quiet except for Dragon Age: The Veilguard in 2024.

EA spared only a few lines for BioWare, instead focusing on three priorities: Deepen Our Core, Expand Our Reach, and Transform Our Business. Battlefield 6 is touted as “a great success” as the company is focusing on Apex Legends modes, Marvel’s Iron Man, and the next Star Wars Jedi game. “Project Gridiron” falls under the EA Sports heading as a social-first, open-world experience from EA’s American football team, with a Fight Night revival currently in pre-production. The company hasn’t forgotten about The Sims, either, and intends to “prioritize [its] efforts on ‘Project Evergreen.’”

Those impacted will be supported “in exploring other opportunities within EA.” EA did not give a job count, and neither the Mass Effect nor the Dragon Age series was declared dead. BioWare’s released games were also not mentioned.

Veilguard, as EA described it early last year, engaged only about “1.5 million players during the quarter,” which was “down nearly 50% from the company’s expectations.” That reception may have played a partial role in the decision, though EA did not say so. Around the same time, BioWare general manager Gary McKay said that only “a core team” was working on the next Mass Effect game and didn’t “require support from the full studio,” as colleagues were matched “with other teams at EA.”

The move is not entirely unexpected, with job cuts being common in the industry, for example, with Microsoft announcing 3,200 Xbox job cuts in July, citing low margins.

EA did not reveal any dates for major titles, but it plans to discuss its direction and the work ahead with staff at its Global Town Hall in November. For now, it looks like EA is doubling down on its core franchises and dropping the studio to refocus on what’s been working.

Google’s tensor processing units (TPUs) — its custom AI chips — now serve AI in production at Meta (creator of the widely used PyTorch AI framework) through a new PyTorch-native version of the SGLang inference engine, announced on Google’s developer blog. A matching version of vLLM, another widely used inference engine, was also announced as open source.

Previously, both engines used Google’s own JAX AI framework to run on TPUs. The new versions allow the hardware to be a native option for PyTorch, mostly without rewriting.

“SGLang-TorchTPU is running in production at Meta today” after “a close three-way collaboration between Meta, Google, and the SGLang team,” said Meta’s PyTorch-TPU lead Zongwei Zhou. That team works at RadixArk, a startup founded by SGLang’s creators, which built the engine with Google and Meta. The engine, he said, gives Meta “a remarkably mature, PyTorch-native serving stack.”

Jana van Greunen, director of PyTorch engineering at Meta, added in Google’s TorchTPU post that Meta “cannot be constrained by a single hardware architecture” and that TorchTPU “enables us to deploy our PyTorch workloads to Google TPUs.” Google said it co-developed TorchTPU with Meta’s PyTorch team.

This is not Meta’s first attempt at using TPUs. Google calls PyTorch/XLA, the older bridge from PyTorch to TPUs, a "predecessor" to the new TorchTPU, and SemiAnalysis reported last year that Meta research teams used TPUs through this bridge from 2020 to 2023 before Meta canceled those contracts. Google’s PyTorch-on-TPU push was aimed mainly at Meta, which did not want to migrate to JAX.

Although it is unclear where Meta’s production TPUs sit, talks last year reportedly included Google Cloud TPU rentals in 2026 with purchases in 2027, and Meta later reportedly signed a multi-year rental agreement.

The announcement came one day after Amazon said it was open-sourcing TorchNeuron, its own native PyTorch backend for its Trainium2 and Trainium3 chips, at the same PyTorch Conference. Both moves appear to be aimed at loosening Nvidia’s software lock-in.

On performance, a tuned vLLM setup serving Moonshot AI’s open-weight, 2.8-trillion-parameter Kimi K3 model reportedly tops 700 tokens per second for a single user on the seventh-generation Ironwood TPU. That speed figure comes from Inferact, the startup founded by vLLM’s creators that helped Google build vLLM-TorchTPU. Its test ran 16 Ironwood chips with speculative decoding, a method of speeding up large language model inference with a small draft model, against vLLM’s published setup on 16 Nvidia GB200s, which reached 452 tokens per second. Its kernels for Kimi K3 and Qwen 3.8 27B deliver roughly 1.4 to 2 times the GB200 baseline’s throughput at small batch sizes without speculative decoding.

SGLang-TorchTPU will keep adding models, starting with DeepSeek V4.1 Flash and Reflection Beam. It's also working toward Day 0 TPU support for new open models, meaning support on release day, by the first quarter of 2027, according to RadixArk. Google, Meta and RadixArk plan to share more at SGLang Summit 2026, Nov. 12–13 in San Francisco.

SSD controller designer FADU’s new File-Semantic SSD (FS-SSD) was announced at the 2026 OCP Global Summit. The new device promises to move the file system into the SSD itself. As detailed in a white paper, this enables GPUs, DPUs, and NICs to open and read files with “no host filesystem, no block layer, and no storage-server CPU in the path.” FADU told Tom’s Hardware Premium it expects partner samples by Q3 2027.

FADU is a Seoul, South Korea-based fabless SSD controller designer. Its FS-SSD technology is designed to handle and improve the control path, as the data path side moved to accelerators years ago. FADU’s measurements show that the file system, plus block layers, can consume about 30% of CPU cycles in a GPUDirect Storage (GDS) random-read workload. It notes that bypass options give up the files, and the company claims its solution promises the best of both worlds.

In FADU’s own preliminary Network File System (NFS) over NVMe test, on a drive built on its FC6161 Gen6 controller in a PCIe 5.0 host, remote file throughput held steady as the server downshifted from what FADU labels 16 cores to just one, maintaining about 460,000 ops/s.

The NFSv3 operations are carried inside standard NVMe commands, and the drive handles path lookup, access control, and file-to-flash mapping. FS-SSD’s performance is remarkable when compared to Linux NFS-over-RDMA, which achieved a third of the ops/s with 16 cores and only 40K ops/s with one core. The technology remains “under active development,” and FADU told Tom’s Hardware Premium it expects Gen6-host results by Q1 2027, with partner samples in Q3 2027.

FADU chooses to use NFSv3 because it’s “small (21 operations), OS- and filesystem-agnostic, and stateless” with low firmware overhead. FS-SSD supports PCIe today, with NVMe-oF over RDMA and TCP working without any new transport needed. Reusing an existing protocol is a smart move, in our view. Under the hood, the file system and flash translation layer are merged with a file layer derived from F2FS. Node and data blocks are aligned with the natural flash pages, sections at corresponding erase units, so that the F2FS node table becomes a “File Map” pointing the node IDs at physical flash addresses.

One big advantage is that the DRAM mapping metadata overhead is considerably smaller: it uses the same amount of DRAM as a standard SSD, ~0.1% of NAND capacity (about 1 GB per TB), which a standard SSD fills almost entirely with its mapping table. Here, most of that DRAM, ~95%, can act as a hot-path node cache.

One garbage collector also replaces two, avoiding what FADU calls the “double GC” of host F2FS, where file-system cleanup and the drive’s own garbage collection amplify each other. Write amplification is also 63% lower versus a host F2FS solution on a mixed sequential and random workload with FADU’s research prototype, the company said. FADU told Tom's Hardware Premium that the prototype runs synthetic fio workloads on NVMeVirt, an open-source software SSD emulator from Seoul National University, so it is not a hardware result.

Most importantly for this method, it ensures host-free access. The GPU builds NFS-over-NVMe commands in queues in its own memory, which could include HBM. Alternatively, a remote SmartNIC or DPU with NVMe-oF target offload can drop commands in the drive’s submission queue. The data goes from SSD to NIC via PCIe peer-to-peer DMA, coming out as RDMA writes. FADU’s explicitly named use cases for this include GPU file reads and checkpoints, DPU-served HTTP content delivery, and a JBoF (just a bunch of flash) file server.

FADU’s numbers for its internal test come from a client and server Intel Core i5-13600K, a CPU with 20 threads that clocks up to 5.1 GHz with 128GB of DDR5, and a Mellanox ConnectX-6 100 Gbps NIC. Synthetic testing is compared using fio with the baseline F2FS and Ext4 on block firmware versus the FS-SSD via a kernel client and an SPDK user-space client. The sequential test is 1 thread, queue depth (QD) 128, with 128KB blocks, while random is at 4 threads, the same QD128, but with 4KB blocks.

These block sizes are typical for client workloads in our experience, so they are a fair measure, with detailed preliminary results in the table below. Against SPDK on the raw drive, figures FADU provided to us, FS-SSD’s SPDK client keeps about 93% on 4K random read and 53% on 4K random write, via fio, with around a 7% and 47% cost for the in-drive file layer. Though the raw drive’s 13,240 MB/s random write is above the ~12 GB/s FADU gives as the NAND’s program bandwidth, those runs likely weren’t at steady state. The Filebench result is particularly interesting, as the SPDK random gains apply to a plain block device too.

This should be the workload most favorable for the technology, as the Filebench file server is metadata-heavy with relatively high host overhead: FADU says it uses 10,000 files in a multi-level tree, mean directory width 20, and a mean file size of 128KB with 50 client threads.

One important thing to recall is that although this test is on a Gen6 drive, the test results are on a PCIe 5.0 host. Therefore, every sequential read config tops out at around 14.1 GB/s, which is roughly the link limit. The testbed also uses a consumer-class desktop CPU, while the one-core NFS server is a showcase example. The kernel client ends up 11.5% behind Ext4 on random read and 5.3% behind on random write, again by our math.

One example of a tough question more generally is: how do concurrent GPU, DPU, and host writers coordinate? How does a kernel mount’s page cache stay coherent with GPU access? NFSv3 storage devices, by the pNFS Flexible File Layout spec (RFC 8435), are “always treated as loosely coupled,” which means “Mandatory byte-range locking cannot be supported.”

Credentials riding in the NVMe command may also face security issues, as loosely coupled devices get only “a level of security equivalent to AUTH_SYS,” NFS’s basic scheme, in which the server trusts whatever user and group IDs the client sends. FADU’s published material also does not describe features such as snapshots, encryption handling, quotas, ACLs, crash handling, and so forth, related to this. Statelessness is what makes it work, but it doesn’t solve all problems, so the trust factor moves elsewhere.

In reply to our questioning, FADU said that there is no cross-host locking, as NFS’s lock manager isn’t implemented. The drive applies each write whole, in order. If two writes hit the same spot, the second one wins; this is “last-writer-wins.” Coordination depends on the clients: kernel-mounted ones get the usual advisory locks among themselves, GPU and SPDK clients coordinate in the application, and at scale a pNFS metadata server handles the coordination. Caching is also handled like ordinary NFS, with kernel clients, or is not done at all, for GPU and SPDK clients. This is stock NFSv3 behavior.

The drive has to check user/group IDs against the file permissions itself. Because those IDs ride inside the command, a client could fake them, but FADU says it closes that issue with capability-based authentication. Each command carries a capability issued by an outside authentication server, plus a code computed with a key shared only between that server and the drive. This is not detailed in its published material. FADU adds that support for the Kerberos authentication protocol is planned. For networked drives, the standard NVMe-oF protections are used, with only pre-approved hosts admitted. A drive trusts a single host’s kernel like any NVMe drive.

However, as FADU described to us, ACLs and other features are missing in the current release, aside from encryption, which in this case is handled by the FC6161’s standard TCG Opal self-encrypting drive support. Power loss is also typically handled with capacitors flushing metadata, the write buffer, and a log of in-flight operations. On restart, the drive replays the unfinished operations, and every write is durable if the drive acknowledges it.

FADU’s longer sights are on producing a JBoF storage solution with no server in front: FS-SSDs, a PCIe switch, and a DPU or NIC for handling NVMe-oF in hardware. FADU’s model puts this at about 42% lower power, about 57% lower cost per 16-drive server, and higher rack density with significantly lower five-year total cost of ownership. The drives would slot in behind existing pNFS metadata servers and could scale. FADU’s controllers already ship with drives such as the SN861, which Western Digital launched and SanDisk now sells, but this would expand the options and solutions it can provide.

Next year should bring real numbers and samples, with the JBoF reference design also expected. There may be an NVM Express or OCP Storage proposal down the line for a file-semantic command set to further cement and mature the approach. FADU has a good idea, is building it on an existing framework, and has a testbed with results and a hardware path forward on its Gen6 controller, with a trust model in mind. A Gen6-host run is now needed to support the company’s claims.

A fanless compute module will head to the Moon for supercomputer benchmarking, AI testing, and additional experimentation by NASA and Deloitte, as detailed in a Hewlett Packard Enterprise (HPE) release. The company’s Spaceborne Computer-4 will run what HPE calls “the first high performance computing (HPC) benchmarks on the surface of the Moon,” riding on an Astrolab FLIP rover to the lunar south pole. The launch is slated for late 2026 under NASA’s Commercial Lunar Payload Services initiative for a Moon Base program mission, in conjunction with a Voyager Technologies Griffin-1 lander.

Named benchmarks include High Performance Conjugate Gradients (HPCG), a supercomputing metric that complements High Performance LINPACK (HPL). AI testing will involve large language model (LLM) retrieval-augmented generation, vision inference, LiDAR processing, and an AI services container for AI app deployment. The LLMs “will deliver insights, analyze visual data, and support autonomous monitoring,” while the LiDAR processing involves mapping, navigation, terrain analysis, and infrastructure development.

Scott Wiest, HPE’s vice president, fellow and global sales chief technologist, said, “The next chapter of lunar exploration will depend on the ability to turn data into insights at the point of discovery.” HPE says “no other company or organization” has conducted such benchmarks on the Moon, with a presumption that no other parties’ planned HPC missions will get there first. HPE also assembled a software suite that handles the link to Earth-side systems and the secure delivery of results.

HPE’s “lightweight, self-contained, and fanless” advanced compute module is “built for space environments,” bringing AI and HPC “to the lunar edge,” as Wiest put it, or the “far-edge,” as HPE calls it. The computer blade is about 10 inches long and about 4 inches wide, about the size of a typical graphics card, and is made from two component cards, as HPE senior director Norm Follett explained on the company’s Technology Now podcast last year.

It includes 1TB of Kioxia storage, a low-power CPU, and a small GPU. The chassis is designed to shed heat into a rover plate, and the overall design is made for the Moon rather than being an off-the-shelf solution like International Space Station (ISS) units. Currently, HPE’s description of the unit lacks hard details on performance targets, power budgets, or chip vendors, but the eventual benchmark results will yield some information.

The original Spaceborne Computer launched in August 2017 on SpaceX’s CRS-12 to the ISS. It also ran HPL with HPCG, surpassing one teraflop, according to HPE. It was rack-installed and water-cooled; the fanless Computer-4 is quite miniaturized in comparison to the 124-pound original Spaceborne Computer. Spaceborne Computer-2, also on the ISS, is made of HPE Edgeline and ProLiant systems with Kioxia SSDs.

NASA will use the opportunity to run its Federated Learning for Unbounded and Intelligent Decentralization (FLUID) AI neural network, trained on data from the Earth, the Moon, and the ISS, coordinating three distinct models. The agency will also test a tuned LLM for semantic processing for handling onboard documents. Deloitte, for its part, will test its Silent Shield, “a new system to detect cyber intrusions” with near-real-time predictive analytics. Testing ideally occurs onboard, as the link to Earth is slow with low levels of bandwidth, Follett explained.

The launch is planned for the fourth quarter of 2026, using a SpaceX Falcon Heavy launch vehicle, SpacePolicyOnline reports. It will take several days for the lander to reach the Moon and its surface. The FLIP rover is designed to operate for one lunar day, or about 14 Earth days, before attempting to survive the night via hibernation, Follett said, making for a relatively tight benchmarking window.

Three contract workers died, and one more is in intensive care after an accident at the construction site for TSMC’s 2nm Fab 22 in Kaohsiung, Taiwan, reports Taiwan’s Central News Agency. The Southern Taiwan Science Park (STSP) Bureau suspects the cause was a broken bolt on a steel connection plate that sent the workers and steel components tumbling. Steel hoisting on the project has been halted, and the STSP has sent labor inspectors to investigate. The accident is not the first of its kind but rather follows at least a half dozen others since September 2024 at TSMC construction sites in Taiwan, according to local reports. Each of those earlier accidents killed one worker.

Local police said that the men were welding a steel beam on an upper floor and fell with it, while the STSP said the workers were performing steel-structure hoisting and installation when a third-floor connection-plate bolt apparently broke.

10 emergency vehicles were sent to the site with 22 personnel, and all four men involved in the incident were taken to the hospital. On-site medical staff gave first aid, but three of the workers died despite resuscitation efforts, and the fourth was moved to intensive care. The workers were employed by a contractor working on the fourth phase of the complex’s construction, and TSMC said the area was within that contractor’s scope of work.

According to the report, TSMC stopped the related construction work on its own and is working with authorities and supervising the subcontractor’s follow-up.

The Fab 22 complex, located in Kaohsiung’s Nanzi District, is part of the science park and is being built to accelerate 2nm manufacturing. TSMC entered high-volume 2nm, or N2, manufacturing in the fourth quarter of 2025, including at Fab 22. The complex has five phases planned, with a total investment TSMC puts at more than NT$1.5 trillion, or about $46 billion. The accident happened on the construction side, not in a producing fab. Kaohsiung’s deputy mayor said construction on Phase 4 began in August 2025, with operations expected in the fourth quarter of 2027.

Business Today reports that TSMC fab construction has increased, from four fabs a year in 2017–2024 to nine a year in 2025 and 2026. The deaths come as the company plans for 13 new leading-edge and advanced-packaging fabs in Taiwan, with company-wide capex of $60 billion to $64 billion this year.

The faster pace has encouraged the addition of a contractor’s safety record as a weight in selection and a plan for a Taiwan Semiconductor Construction Engineering Safety Association with construction partners. TSMC Chairman C.C. Wei said at last year’s shareholders meeting that safety cannot be compromised, and the company’s 2025 annual report said it will keep investing in fabs across several locations in Taiwan “with a strong emphasis on construction site safety.”

Cliff Hou, TSMC senior vice president and deputy co-COO, told Business Today that increased worker count and overlapping construction have raised the risk, requiring careful supervision, and that TSMC’s contractor lost-time injury rate had fallen about 42% from last year’s high as of late May, when the publication toured the Nanzi site to see the overhaul. It’s too early to call the program a failure, with the cause as yet unknown.

The accident comes less than a week after an explosion killed two people at Intel’s chip plant in Israel, though that was an operating fab rather than a construction site. Both accidents come as chipmakers race to meet demand, with global chip sales passing $1 trillion through August, according to the Semiconductor Industry Association.

The STSP’s findings will determine what penalties, if any, will fall under Taiwan’s Occupational Safety and Health Act, while it assists the victims’ families. No date has been given at this time for that or for the Phase 4 steel hoisting restart. Nor has TSMC commented on any schedule impact.

The game of Minecraft is no match for a team of four Gemini 4 Argon agents, as they were able to defeat it in 27 hours with 2,783 self-written programs, a paper from Google DeepMind reveals. The agents did die 605 times, even on Easy, and about half the run was spent fighting the Ender Dragon, the final boss of the game. The run finally came to completion when the End was solved by stacking dirt to reach the boss’s crystals, at an estimated cost of around $520 in tokens.

The experimental run was designed from the get-go with one goal: kill the Ender Dragon. The playthrough involved a random, shared survival world on Easy with four agents — a fifth agent existed only for reporting — from Gemini 4 Argon, Google’s latest frontier model. Each agent had its own player through the open-source Mineflayer JavaScript library for Minecraft bots, but they were able to coordinate through in-game chat and shared notes. Every program used in the run was written by the agents themselves, and the emphasis is on coding and teamwork rather than game-playing.

The authors say this is the “first end-to-end autonomous completion of Minecraft by AI agents,” at least “to our knowledge,” qualified by the use of Mineflayer “without pre-scouted seeds or other game-specific tools written by humans.” Mineflayer tells the agents where blocks and creatures are, with a pathfinding plugin to plan routes. There was “no human input during the run” and “no one assigned roles or wrote game logic.” The run, starting with the first program and ending with the dragon's death, took 27 hours and 14 minutes.

Although the agents were not given roles, within about 10 minutes a division of labor was proposed in chat by bot janesick. Bot Auratian offered an alternative plan while Bot Gyldenia acknowledged it. The roles ended up being: Gyldenia for food, beds, and flint; Bulicame for diamonds; Janesick for iron and tools; Auratian for the Nether portal. Moments of losses, such as a Ghast fireball destroying dropped items, led the team to diagnose the cause and write rules to prevent it in the future.

Finding the stronghold involved janesick, who threw two Eyes of Ender from different spots and sampled each eye’s flight once every 50 ms, triangulating the location. Carrying the eyes involved its own dire moment when Auratian drowned during the task, but the spot was noted, and the eyes were rescued.

The eventual fight with the dragon led to 69 deaths, and the ten crystals kept regenerating the boss until Auratian discovered they could use dirt pillars to reach the crystals. Four hours and 40 minutes later, all ten crystals were downed, and the dragon was dead 39 minutes after that.

The agents operated by writing short JavaScript programs, almost 2,800 in total, with 42 helper functions kept alive between programs, while a Mineflayer bot ran them in the shared world. Text was returned with status data, not pictures. This is a shared approach to the non-screenshot GPT-6 Astra clear of the Orc starting zone in World of Warcraft earlier this month. AI agents playing games is an ongoing trend, with Pokémon Red probably being the most popular, a game defeated in multiple ways, including with a Jev decision model layer.

Minecraft has also been a popular target, and the authors admit this, highlighting two earlier community dragon kills: a planner with an action-selection model on a fixed speedrun seed in Peaceful mode, and a single Claude Opus 5 agent that used 37 ready-made, high-level tools on Normal, versus Mineflayer alone for the Gemini team. AI Bengineering’s Claude run, relying mostly on Opus 5 at high effort, took 3 hours and 56 minutes from start — “no human input after the prompt” — to kill with 388 tool calls and only one death. The cost in that case, at API-equivalent rates, was about $93.

Google’s Minecraft run, using Gemini 4 Argon’s 50% introductory pricing, which runs from initial API access that followed the model announcement through Nov. 30, cost more than half a grand; at normal pricing, that’s more than a grand. A GPT-6 Astra Portal run last month, which took about 24 hours, came in at $571 in tokens.

Google’s run took about 1.35 billion input tokens with 91% served from cache. About 24,000 model calls involved around 16 million output tokens, a quarter of them thinking. In total, if we’re also including the observer agent, the session would be estimated at $810, or $1,620 after the promotion, at list prices.

Each player is driven by a “general-purpose Gemini 4 Argon coding agent,” which is a fancy way of saying that it’s not specialized for Minecraft. Gemini 4 Argon itself is a frontier model for “real-world software engineering, enterprise knowledge work like legal and finance, and cybersecurity defense,” according to a company blog. With Minecraft, 22% of the agents’ programs ended in an error, with more than 600 deaths.

Although the model was used for a game here, the run was designed to show that Argon is capable of “complex, long-horizon workflows” for complex real-world tasks and agent coordination. Such long projects can involve decompiling a game back into source code, as we covered recently with a Modern Warfare 2 rebuild that now has 83% of its functions matching the original byte for byte.

A Russian military satellite, Cosmos 2612, has closed to roughly 3 miles, from a previous distance of more than 200 miles, of the U.S.-owned radar satellite that operates in a fleet that supports Ukraine, Axios reports. The unapproved rendezvous in low Earth orbit, which astronomer Jonathan McDowell says may be the first of its kind, raises alarm in the West. The position change, which was likely not an accident as fuel is scarce, is probably a provocation and an attempt to spy on the satellite.

LeoLabs said in a statement Friday that the movement “appears to be a deliberate approach” toward ICEYE-X36, with uncertain intent and behavior that “warrants continued monitoring.” Roughly 3 miles is too close for comfort in satellite terms: there is no strict legal limit on how close satellites can get, but countries generally keep at least 6 miles (9.7 km) apart, University of Mississippi space law professor Aaron Brynildson told Axios. The approach was made without the owner’s consent, and Russia hasn’t said what the military satellite carries.

Some clues may come from the target’s operational purpose. ICEYE-X36 is a synthetic aperture radar (SAR) satellite which can image through cloud cover and at night. It was launched in March 2024 on a SpaceX Falcon 9. It’s registered to ICEYE US, the U.S. arm of the Finland-founded company. The satellite, which is in a roughly 545 km (339 mi) sun-synchronous orbit, is part of a fleet that has supplied Ukraine with information since 2022. This includes a deal earlier this year with a customer in Ukraine’s defense ministry, but a Ukrainian official told Axios it’s unclear whether ICEYE-X36 itself supports the country; ICEYE and the Defense Department declined to comment.

In May, the majority of the six military satellites Russia launched in April via a Soyuz-2.1b, Cosmos 2609–2614, shifted their orbits about 0.8 degrees to match X36’s orbital plane. Cosmos 2609 passed within 2.5 km (1.6 mi) on May 26. Cosmos 2612, on the other hand, drifted off X36’s plane by about 0.24 degrees by Sept. 30, up to about 28 km side to side, according to Greg Gillinger, a space analyst with Integrity ISR.

Then, Cosmos 2612 made separate burns from Sept. 30 through Oct. 16 to match altitude, eccentricity, and orbital period, Dutch satellite tracker Marco Langbroek wrote. By Saturday night, he estimated from public orbital data, it was within “a few hundred meters or possibly (much) closer.”

These movements appear deliberate and cost a lot of fuel, which the Center for Strategic and International Studies calls “a limited resource on a satellite.” Close-proximity work can be benign, it says, but policymakers should assume the Russian satellite “could take an action that threatens the commercial satellite,” and the U.S. and Europe should decide how to respond to any hostile act in space and make a statement on the decision. Back in July 2020, Russia’s Cosmos 2543 released an object at up to 186 m/s (416 mph) relative to itself, an action which was condemned by the U.S. and U.K.

Intent was less clear earlier this year, when McDowell told Meduza the orbital data showed no sign of the stable, close distance that tracking ICEYE-X36 would require. Now, he says it is an unapproved meeting and is not alone. Gillinger says the setup “removes any remaining doubt for me that Cosmos 2612 is interested in ICEYE X36.” Langbroek adds that “I was skeptical” at first but now calls it “completely non-consensual,” though he cautions it would be difficult to pin any X36 failures on 2612’s actions.

In a Reuters report less than two weeks ago, ICEYE CEO Rafal Modrzewski said the company moved its satellite after May, only to draw more Russian maneuvers, which Germany’s Space Command head, Maj. Gen. Michael Traut, described as “chasing.” Belinda Marchand, chief scientist at U.S. space intelligence firm Slingshot Aerospace, added that the moves may have been meant for surveillance, to prepare for future interference, or to signal capability. Western officials reportedly describe such trailing as a way to gather intelligence and test the West’s tolerance.

No statement from Russia is on record. Gillinger also told readers to “watch Cosmos 2611 and 2613, whose planes are converging on ICEYE X37’s,” with crossings expected around Nov. 6 and Nov. 15.

MIT engineers have built a soft, wearable shape-sensing sheet with self-tracking movement that could be useful for controlling games, virtual reality, and physical therapy applications, reports MIT News. The technology, which leverages optical fibers to track the sheet’s own 3D shape, keeps its error below half a centimeter in lab tests. Qifan Yu, an MIT mechanical engineering graduate student on the team, put rigid-sensor designs at around 1 to 2 cm and called the result “at least on par with existing technologies.” The sheet also still works even when damaged, but the fibers remain thicker than ideal for garments.

The news follows a paper, “Toward fully soft and multifunctional shape sensing via optical waveguide arrays,” recently published in Advanced Intelligent Systems. It details that the waveguides respond to bending in both directions, “bi-directional,” with the array laid out to discern shapes. Combined fiber responses mean fewer sensing elements are needed, and that can also improve damage resilience. The fibers respond to pressure, so they can sense external force, such as a press on the forearm in a physical therapy demo.

Normally, a plain fiber, a transparent core inside a light-trapping cladding, will have less light reach the far end when bent; measuring the light output helps measure the bend. MIT’s changes here include using a flexible rubber core instead of glass, with black-dyed cladding. One side is roughened intentionally so that bending the fiber toward that side, or toward the opposite side, causes different amounts of light to be lost. This enables directional sensing.

Many such fibers are embedded in a silicone sheet, with an LED at one end of each fiber and a light sensor at the other. The sensing surface is fully soft, but the sheet doesn’t stretch as a whole. An external circuit board handles the data collection with an algorithm translating it into a full sheet and 3D shape. The 14 waveguides are each 160 mm long in two layers of seven, zig-zagged within a 16 x 16 x 0.5 cm silicone sheet. The electronics remain at the edge, including analog-to-digital converters that feed microcontrollers over I2C. The reconstruction runs in MATLAB about three times a second, a rate that includes sensor sampling, data logging, and plotting.

To pick the layout, the team first simulated sheets with different waveguide arrangements: it generated the light output each fiber would give for a known shape, ran those readings through the reconstruction algorithm to estimate a 3D shape, and compared the estimate with the known one. One zig-zag spacing pattern had the closest fit. In simulations, between 3 and 20 waveguides per layer were used at angles of 0 to 35 degrees on six target shapes, with 10% added noise, over 30 trials each. The researchers discovered that angling the waveguides improved accuracy more than adding additional ones.

Resilience was tested with a few fibers cut or disconnected, with the rest still able to reconstruct the overall shape. In simulation, the error stayed under 0.3 cm with up to three of the 14 waveguides disabled, and rose to about 1 cm or more from five on.

A real sheet was then built on the pattern findings and put to the test with diagonal folding. For accuracy, the sheet was laid over three 3D-printed molds of known shapes, with the metric being the root-mean-square distance between real and reconstructed surfaces: 0.37, 0.28, and 0.45 cm. The force sensing does not have a calibrated force reading to tell how hard, and this detection runs separately from the shape mode. Each wearable demo was done by one author on their own body, with a simpler scaling method for wrist and elbow angles, because stretching at those joints throws off the shape algorithm, with no comment on comfort.

Yu said the setup targets fully soft sensing surfaces, so it’s potentially safer around people. Kaitlyn Becker, an MIT assistant professor of mechanical engineering and co-author, said the team hopes to build tools that help physical therapists track and quantify a patient’s progress over time, comparing sessions more precisely. Outside of this, the tech could also be used in virtual reality to mimic motion or could be used for the teleoperation of robots, or even just soft robots.

As thinner fibers would have a wider applicability, the researchers plan to target a thinner sheet first. The 1 mm thick fibers of today could get as thin as tens of micrometers, thinner than a human hair. A higher fiber count could then make for smart garments. They also suggested future work could focus on a faster solver rather than the general-purpose one in MATLAB, more waveguide layers and narrower waveguides for better detail with thinner sheets, a separate sheet to gauge force and shape simultaneously, and stretchable electronics.

More than 300 local data center construction moratoriums haven’t had a massive impact on planned buildouts, with only three projects at about 2.3 out of 21 gigawatts (GW) of data centers in moratorium areas likely to be delayed, with a total of 38 GW projected to come online next year, SemiAnalysis shared on X. Per-project audits of the moratoriums indicate that they tend to miss the site, the permit, or the timeline.

The crux of the report is that, while everyone thinks the moratoriums are killing the U.S. buildout, its forecast has “barely moved over the last 12 months.” This forecast includes 38 GW of U.S. data center IT capacity in 2027, which is more than double that of 2026. Of that, 22 GW is under vertical construction, and the other 16 GW is mostly financed, with site work being done. The enacted local moratoriums cover about 20 GW with only about 1.5 GW of it delayed; New York’s pause adds 0.8 GW more. “We think moratoriums COULD delay the buildout, but they just aren’t yet at scale.”

The firm defines a moratorium as a “temporary legal pause,” and almost always a “freeze on accepting new applications.” More than 400 local instruments are tracked across 17 states, the enacted ones including a few permanent zoning bans, as of September. Four states acted in under two months this summer: New York, Texas, Pennsylvania, and Oregon. To test each active restriction against the records of thousands of projects, the firm’s analysts worked alongside “an army of state-of-the-art research agents.”

Several reasons are given for moratorium ineffectiveness, starting with the fact that they don’t revoke existing approvals. Short ones may expire before later projects need approval, and litigation or equipment lead times may already set the schedule. A moratorium moves the delivery date only if every condition holds, including that it reaches the parcel, is in force, overlaps the timeline, and covers the use in a way the project can’t work around. Capacity already under construction or fully permitted is also out of reach.

For example, Michigan has 45 enacted moratoriums but effectively zero pipeline exposure, and a Google campus there sits on industrial land already zoned for data processing. The firm says SpaceX’s planned data center in Brownsville, Texas, is on land the city removed from its limits and thus out of reach of the city’s moratorium. For a moratorium that did work, a township adopted a pause before NorthPoint, in Pennsylvania, filed for its special exception, with local approval pushed to next year. The company is still pursuing it.

The 2.3 GW figure is also incomplete, as it leaves out the Texas Commission on Environmental Quality (TCEQ) pause. Texas Gov. Greg Abbott told the TCEQ to issue no permits for data center projects. Law firm Bracewell says this applies whether a project is in the Electric Reliability Council of Texas’s (ERCOT) queue or not, and expects the pause to last until ERCOT finishes its review in mid-December. Pauses like the TCEQ’s, and how they play out, could impact buildout forecasts.

The post quotes another by The Economist’s Archie Hall, from a trip that covers Michigan and Ohio, with the reporter stating that data center moratoriums are “much more bark than bite” for the time being. He puts the bigger risk at deterring newer projects, though he guesses that affects where data centers end up more than whether they get built. His impression is that politics also plays a role, and according to the firm’s poll in August, more Americans have a negative rather than positive impression of data centers.

The analysis concludes that moratoriums would need to be “materially more widespread and restrictive” to delay the buildout. On the firm’s weekly podcast last month, Jeremie Eliahou Ontiveros, one of the report’s authors, said the firm would be worried by a strict, state-level moratorium that blocked even off-grid projects, citing Texas as an example. New York Gov. Kathy Hochul, in addition to Abbott, also found ways to bypass their legislatures for pauses they control and can revoke. The next move to watch is the TCEQ’s compliance report to Abbott’s office, due Monday.

DJI has delivered a battery-swapping drone dock, the Dock 4, with an automated 25-second swap this week, according to a company press release. The dock bypasses the normal recharging process, which would take about 30 minutes, and DJI promises a turnaround of under 45 seconds from landing to takeoff. The drone-in-a-box solution is the first of its type by the company, although not in the industry, and is aimed at applications like emergency response but is not FCC-authorized or for sale in the U.S.

The company emphasizes the safety angle, pitching the Dock 4 as a “dock-as-a-first-responder (DFR)” solution. Its product page calls it “Always There, Always Ready.” Swapping the battery takes less than half a minute, and the drone is back in the air within 45 seconds of landing. The dock also charges two 925 g battery packs, rated at 260 Wh for 400 cycles, at once, estimated to take 27 minutes to get each from 15% to 95%.

The packs also double as backup power, rated at about 4.5 hours each, in sequence. Additionally, with at least two packs loaded, the dock is able to continue swapping even when grid power is lost, although backup power doesn’t charge the packs. This configuration should enable a drone to handle back-to-back calls even in less-than-ideal circumstances. The new dock, 66 kg bare, also has the same 400 x 400 mm mounting holes as the Dock 3, but it only works with the Matrice 5TD drone and requires the DJI O4 Ground Station.

The Matrice 5TD drone is rated for almost an hour of forward flight, measured from 100% to 0% at 15 m/s and with no payload, with a few minutes less of hover time. It can move at up to 21 m/s, or 47 mph, but only in “FlyTo” tasks. It carries three 50 MP cameras: wide, 70 mm equivalent medium telephoto, and telephoto at 252 mm equivalent, which DJI calls 11x. It also has 1280 x 1024 native thermal and 2560 x 2048 in DJI’s UHR infrared mode, color night vision without a spotlight, and a laser rangefinder up to 3,000 m.

For sensors, it has rotating LiDAR, mmWave radar facing forward, up and down, and six-direction vision, and DJI says it is capable of detecting power lines at night. On-board AI allows for the detection of 17 object types, “such as cars, boats, or animals,” and DJI FlightHub 2 can search the feed by text or image and send alerts. The dock and drone are rated for temperatures from minus 40 degrees to 50 degrees Celsius (minus 40 to 122 degrees Fahrenheit) with IP56 and IP55 ratings, respectively. The drone is rated for winds up to 12 m/s, or about 27 mph.

For payload, the drone carries up to 450 g across three mounts for a speaker, spotlight, and parachute. The previous model, the Dock 3’s Matrice 4TD, has a lower-resolution 640 x 512 thermal camera, a 168 mm telephoto, a shorter 1,800 m laser range, and is only good down to minus 20 degrees Celsius (minus 4 degrees Fahrenheit). The drone upgrades are nice, but the new dock capabilities are the real selling point, especially for the intended applications. Currently, DJI partners in China are taking orders for a kit with the Dock 4, Matrice 5TD, and O4 Ground Station at 167,999 yuan, or about $25,000, for the hardware alone.

The new dock and drone sound great for other markets, but DJI’s own spec sheet has no FCC figures. This is likely because the FCC added all foreign-made drones and their critical components to its Covered List in December of last year. New models can’t get FCC authorization or be sold in the U.S. unless the Department of War or the Department of Homeland Security determines they don’t pose a security risk. DJI sued the commission earlier this year.

A separate FCC proposal published in August could pull previously authorized foreign drones that carry LiDAR or thermal sensors from sale, along with previously authorized docking stations. The FCC’s docket shows no final order on it as of Oct. 17, and the proposal would give sellers 180 days after Federal Register publication to stop importing and marketing covered gear.

The decomp.dev community that tracks and centralizes game decompilation progress is shutting down its public index and leaderboard, claiming in a site update that the acceleration of AI has damaged the decompilation community. The creator, who goes by @encounter, points to abuses related to AI usage, such as AI helping forks “finish” others’ projects and a general attitude of rushing to complete PC ports, often with little regard to quality. Simply banning AI-assisted projects is a difficult task, as not all of them have the same standards, and @encounter feels it shouldn’t be the role of one hobbyist to decide what does and doesn’t stay on the leaderboard.

The decision was made because AI greatly speeds up decompilation “in a significant way,” especially with human guidance, but misuse of the technology has broken the community aspect. AI has made the progress percentages on decomp.dev easier to push up. As a result, the site’s index and leaderboard are now “causing more harm than good,” as the competitive spirit has been corrupted. The scene has become “a hollow numbers game” where people throw AI usage at things “to make number go up.”

The site was created in 2024 “as a way to centralize matching decompilation progress” and to grow a community around it. Each project page shows game progress with its history. The goal of matching decompilation is to have hand-written source code that could compile back to the same machine code as the original game. The site’s creator is a GitHub maintainer of decomp-toolkit, a GameCube and Wii decompilation toolkit, and objdiff, a local diffing tool for decompilation projects.

Matching decompilation used to be a “brutally difficult, time consuming [sic] task,” taking years for many games. Better tools and community knowledge sped up the progress. AI worked its way in through the years, but results were generally mixed. Things changed earlier this year with Claude Opus 4.6 and GPT-5.4, which seemed to know the community’s tools without being told; encounter writes that it was “clear that the models were being trained on matching decompilation.” However, the models’ results still needed “a significant amount of human cleanup,” and the cost per task was “prohibitively expensive relative to the results.”

More recent models, with OpenAI’s GPT-6 Astra specifically named, are much better at handling complex directions and at writing natural code and are “exceptionally good permuters.” The models can stay on task longer, finish tasks more quickly, and in general operate more cheaply. However, applying the models without guidance means that the code can compile to the same machine code but wouldn’t pass as the original developers’ work. Humans learning to apply the technology better is a pattern in this space, as Maurice Heumann’s Modern Warfare 2 decompilation project showed; in that case, Heumann’s agents tried to cheat the byte-for-byte check itself, but then Heumann adapted.

The projects, which are open source and welcome contributors, have been tainted by “bad actors” who abuse that openness. Some original projects avoid AI for legal or ethical reasons, and AI forks may put “little to no effort” into contributing back. Because AI has improved, anyone with an AI subscription can now create ports that work “at a basic level,” using tools “written by talented humans.” This allows opportunists to race out half-working decompilation ports. Ports can be fun, but decompilation is “primarily for research,” and the creator calls out YouTubers, dubbed “Sloptubers,” and subreddits like r/decomps for falsely synonymizing “decomp” and “PC port.”

The site was originally built “to gamify decompilation,” a fun way to stay motivated back when “every fraction of a percent took real human effort.” While the widening of the community has had positive aspects, it has also brought “slop,” which is admittedly “hard to define, and even harder to moderate,” so an outright ban on AI-assisted projects isn’t practical. Judging and policing “hundreds of projects” is too difficult a task. AI-generated code has made headlines in other open source areas, such as with Linux.

Existing projects, some of which have achieved 100% decompilation progress, such as Super Smash Bros. Melee and Animal Crossing, will keep on reporting, and their pages and history will remain. However, no new projects may join, and nobody may rebuild the site from its code. There is no successor named, and no shutdown date. Decompiling goes on, and AI is making it even faster, but the percentage scoreboard is gone.

YouTuber hardware enthusiast and Thermal Grizzly boss der8auer tested a two-year-old liquid metal thermal interface material (TIM) application with an electron microscope in his new video, discovering that it doesn’t dry out. Instead, the gallium bonds with the copper in a reaction to form a solid compound. On copper, that layer’s heat conduction performance is about one-quarter of the bare metal’s, and nickel plating keeps it about 10 times thinner.

His test showed the TIM as liquid after one hour, no liquid visible with crystals everywhere at the two-month mark, and then unchanged after two years. “After a total of two years, this honestly did not change further,” he said. The test relied on storing the setup in a vacuum or a nitrogen-filled box between sessions to avoid oxidation.

The TIM in question is an alloy of gallium and indium, often including tin, which is liquid at room temperature (Thermal Grizzly sells its own as Conductonaut); gallium melts at about 30 degrees Celsius, with the gallium-indium-tin mix melting at only 11 degrees. Improving cooling at the interface bottleneck is becoming a real issue as heat per surface area continues to rise. His examples are the RTX 5090 and RTX 5080, which he says have “twice” and “three times” the power density of the 8800 GTX.

How the liquid metal reacts depends on the cooler material. With aluminum, the gallium travels along the grain boundaries once the oxide layer is broken, and this weakens the metal. His demo on a scrap 2 mm aluminum sheet showed surface swelling after about five minutes, and it became brittle within half an hour. This reaction has been “common knowledge for a very long time.”

With copper, the liquid metal on the cold plate of Thermal Grizzly’s new stainless steel water block can’t be wiped off with isopropyl alcohol or acetone after less than five minutes. The gallium bonds with copper to form CuGa2, one copper atom to two gallium atoms, with the leftover indium and tin forming other solid areas. This makes the film look like it is solidifying. CuGa2’s heat conductivity is rated at about 100 W/mK versus copper’s roughly 400. Since CuGa2 stays solid up to about 254 degrees Celsius, “you will not be able to melt it again.”

The layer grows about 1 micrometer a day until it reaches about 50 to 100 micrometers, depending on temperature and how much gallium is available; his example of pure gallium between copper plates at 70 degrees Celsius shows about 4 micrometers over 96 hours. The liquid metal “doesn’t really dry out”; it “reacted chemically and it formed a solid compound,” so the metal is still there in another form.

On nickel-plated coolers, the gallium forms NiGa5 instead, one nickel atom to five gallium atoms, which is also solid at room temperature. The nickel plating stops the layer at about 10 times thinner, at 1 to 5 micrometers, or 5 to 10 micrometers on his slide, but NiGa5 conducts heat worse than the copper-gallium compound. However, nickel is “most of the time superior” in his estimation because much less gallium gets absorbed into the surface, and it protects the copper underneath.

Removing the residue is tricky, and he recommends Thermal Grizzly’s TG Metal Polish & Restore, with a chemical that lowers gallium’s surface tension. The company’s Sept. 30 blog post describes it as a surfactant that binds gallium to stop it from re-sticking. It costs $22.11 direct for 30 g of paste, a polishing pen, and microfiber cloths. His demo showed fresh film coming off bare copper. A PC Games Hardware forum user used it to clean an Aqua Computer block that had run liquid metal on a delidded Skylake-X since 2018, with removal taking about an hour.

This isn’t a TIM for the average user, and he recommends that it should “stay in the enthusiast bubble,” intended for very high power density components like a manually overclocked CPU. Thermal Grizzly aims to replace nickel with new coatings, “hopefully next year.” It also plans to release a new version of its KryoSheet graphene pad for bare dies shortly, which he says is maybe three or four degrees worse than liquid metal but worth a try, “especially if you look at the pricing.”

For cost, he points out that his company pays almost 10 times as much for gallium after five years, from €300 per kilogram to €2,500–3,000. Prices have more than doubled since the start of 2025. China supplies 99% of the world’s gallium, and its ban on gallium exports to the U.S. is suspended only until Nov. 27, 2026, with export licenses still required.

A Chinese rival to the DGX Spark and the Ryzen AI Halo, at least on paper, has emerged with Sipeed’s announcement of the MaixStation. The system, built on Axera’s new AX8860P, is in the same memory class with 128GB of LPDDR5X on a 256-bit bus at 273 GB/s. Sipeed told Tom’s Hardware Premium it expects the 128GB model to cost around $3,999, with launch discounts on Kickstarter, putting it level with the 128GB Ryzen AI Halo and well under the DGX Spark’s current MSRP of $6,950. Sign-ups are open now on Sipeed’s MaixStation page ahead of a Kickstarter campaign at the end of the year, with units shipping within three months after it closes. The NPU toolchain is due by the end of this month.

The AX8860P is a 16-core Arm Cortex-A55 part with an in-house NPU rated at 256 TOPS at native FP4 with no sparsity. The chip is produced in the 6nm process, Axera says. Sipeed claims the system has 25% faster prefill and 30% faster decode than the DGX Spark when running Qwen 27B (the company did not disclose which specific model, but later details that it expects a single MaixStation to run Qwen 3.8-27B) from a single node.

In its email, though, the company put its MaixStation about 10% ahead on both prefill and decode when compared to DGX Spark, with FP4 on each machine, with speculative decoding off, and said newer runs with a wider lead aren’t official yet. It teased the new product on its X account, showing a photo from the AX8860P’s announcement at an industrial fair in Shanghai on Tuesday.

For comparison, the DGX Spark also comes in 128GB at 273 GB/s with another SKU at 64GB, the two models priced at $6,950 and from $4,999. The former has been on sale since October 2025, at its current price since Oct. 2, and the latter is expected through partners on Oct. 23. For AMD, its Ryzen AI Halo has a 192GB Max+ PRO 495 model at 273 GB/s, released earlier this week at $7,299.99 for the Linux version, and the 128GB Max+ 395 model with 256 GB/s at $3,999.99. In all cases, 256-bit LPDDR5X is used, so the salient differences are memory capacity, compute, and software.

Memory is also a big share of what these systems cost: the best U.S. price for a 128GB DDR5 kit was $3,399 in August, and TrendForce expects conventional DRAM contract prices to rise another 10–15% this quarter. As for its unit prices, Sipeed says it used current DRAM prices rather than stock bought last year. It also suggested buyers could supply their own SSD, which could cut the price further, clarifying that the MaixStation takes a standard M.2 2280 drive rather than the Spark’s less common 2242.

Software-wise, the Spark ships with DGX OS, which is Nvidia’s build of Ubuntu 24.04 LTS, with CUDA and Nvidia’s AI software stack preinstalled. AMD validates ROCm, drivers, models, and frameworks together as a “Best-Known Configuration.” Neither the Spark nor the PRO 495 ships with Windows yet, though AMD says Windows versions are “coming soon,” and the Max+ 395 model already offers Windows 11 Pro. Sipeed, aside from its upcoming NPU toolchain, claims support for vLLM, SGLang, and PyTorch, with Axera adding ONNX, Hugging Face (HF) model formats, and an OpenAI-compatible API. MaixStation itself ships with Debian 13 and Linux 6.18, and Windows support for the PCIe card will depend on demand, Sipeed says.

Chinese solutions already exist on AMD silicon, such as GMKtec’s 192GB Evo-X5 Pro at $6,799 to $7,099. There’s also Minisforum’s MS-S1 Max-P495. What’s new with the MaixStation is the Chinese silicon underneath.

The Axera AX8860P, as recently launched, has, in addition to the above specs, PCIe 5.0 support, 64-channel video decode with 16-channel encode, and support for multiple form factors, including a single-slot, four-chip PCIe card capable of running up to 512GB of memory, with mini and pocket PC products planned. Like the eight-core AX8850 in Radxa’s and M5Stack’s M.2 accelerator cards, it pairs Arm Cortex-A55 cores with Axera’s NPU, now with twice the cores and up to 128GB of memory instead of 8GB. Two- and four-chip cascades reach a theoretical 512 and 1,024 TOPS, respectively, at a claimed scaling efficiency of about 80%. The CPU, against the Spark’s Cortex-X925 and Halo’s Zen 5, is small and in-order. It’s sufficient for the NPU but potentially more limited for other tasks.

The box itself measures about 11 × 11 × 3 cm and draws about 40W in typical use, powered over USB-C, according to Sipeed. Its ports include 10G SFP+, USB-C, an M.2 2280 slot for a PCIe 5.0 SSD, and an MCIO 8i connector for linking a second unit.

Sipeed says the MaixStation supports all configurations, that’s single, dual, and quad node, plus any “PCIe card mode for any card count you want.” The interconnect in use is a 256 Gbps C2C connection (up to 384 Gbps) “without [an] extra switch needed, and [up to] 8-node.”

The contrast is with the Spark’s QSFP ports, and Nvidia’s datasheet says linking four Sparks “requires [an] external switch.” The math, at 32 Gbps per lane, works out to 256 Gbps with the default eight lanes and 384 Gbps with the maximum of twelve. Remote-access test units and a few review units will follow during the Kickstarter campaign, the company told us.

Sipeed also commented on the openness of the platform, saying, “Yes, bsp sdk is open, you can use AI to port any distribution on it!” Sipeed has previously sold Axera boards, with products dating back to 2022 using the AX620A, AX650N, and AX630C.

The claims of the MaixStation being faster in some workloads are coupled with Sipeed saying “In fact you need [to] ask why DGX is so slow…” with potential financial implications, as Nvidia “just [wants to make] more money from users.” When an X user argued that Sipeed must be using extreme quantization at that bandwidth, the company suggested that the Spark’s specs may be overstated.

By our math, the decode claim is plausible with a 4-bit 27B model, which sits at about 13.5GB. Performance on comparable machines tops out near 20 tokens per second, which means around 270 GB/s. Prefill, which is compute-bound, is a harder sell, but Sipeed stated that “DGX Spark 1000TOPS is fake ‘sparse.’” That 1 PFLOP figure does rely on sparsity, but the DGX Spark’s dense rate of about 500 TFLOPS is still around double the AX8860P’s 256 TOPS.

Axera’s current stack has Pulsar2 as the NPU compiler and toolchain, with version 8.0 on HuggingFace last week, and the V7.0 docs already list the chip as the AX8860. There’s no operator support list for the chip yet, and the docs’ LLM chapter for older chips lists weights down to 4-bit integers but no FP4. Neither the ax-llm runtime nor AXCL, the host-side PCIe driver and runtime for Axera’s cards, lists the chip yet. Sipeed says the end-of-month release is AXDSL, a kernel-programming language, plus the Pulsar2 source code, and that SGLang and vLLM run on a custom backend built on it, so Hugging Face models run without a conversion step.

Enthusiasts are already eager to know the final specifications and pricing for the different models. On paper, as far as local LLM machines go, the MaixStation matches the Spark on memory size and claimed bandwidth, and the Max+ PRO 495 Halo on bandwidth alone. Testing performance claims will also have to wait for the toolchain and sample machines land, hopefully before the end of the year.

Two workers have been confirmed dead and another seriously injured after an explosion at Intel’s Kiryat Gat plant in southern Israel on Wednesday, The Times of Israel reports. Police suspect a gas cylinder malfunction caused the explosion, and Israel’s Fire and Rescue Services said the fire involved nitrogen trifluoride (NF3), a toxic gas mainly used to clean the process chambers of chipmaking tools. So far, Intel hasn’t made any statements about the victims or about any potential production impacts at the site.

The site houses Fab 28, which, per Intel, makes “processors, 5G, and AI products” on Intel 7, formerly 10nm Enhanced SuperFin. Intel 7 products include 13th and 14th Gen Core “Raptor Lake,” 5th Gen Xeon “Emerald Rapids,” and the I/O die of Xeon 6 “Granite Rapids,” although these are not explicitly linked to the site. Fab 38, adjacent to Intel’s existing Kiryat Gat fabs, was announced in December 2023 with a $3.25 billion Israeli grant but has been paused since mid-2024. Intel reportedly considered closing Fab 28 in July 2025, but no closure decision has been announced.

The Kiryat Gat police commander at the scene laid out the sequence: a blast occurred during a material transfer into the factory’s tanks after one truck had disconnected and another connected. At least eight Fire and Rescue Services teams, including hazmat, searched for trapped people, contained the fire, and monitored the hazardous substance.

“At this moment, I cannot point to any suspicion of criminal activity or negligence,” the commander added. Magen David Adom, Israel’s national emergency medical service, said two of the injured underwent resuscitation efforts and all three suffered severe burns. Ultimately, one of the injured was pronounced dead, a second later died of their wounds, and one remains hospitalized in serious condition inside the ICU, based on a statement from Soroka Medical Center in Beersheba.

The gas, although hazardous if inhaled, is not flammable. It’s not clear if the trucks were delivering NF3 or if it was directly involved in causing the explosion. Once the fire was put out, crews kept cooling the scene to prevent a secondary incident, and the commander said things appeared to be under control, with no sign so far of further leaks and no need to evacuate residents or factory workers. Kiryat Gat Mayor Kfir Suissa told residents to stay away while crews worked and added, “There is no danger to the public.”

At the time, there was no word on possible production delays, but these would be problematic as Intel 7 capacity was already tight. Last year the company’s CFO said that Intel 7 and Intel 10 constraints had limited its ability to meet demand, with shortages expected into 2026 with server wafers getting priority. Intel reports third-quarter results on Oct. 29 and will hold a call to discuss them, although the company has not mentioned whether it will address the explosion.

This year’s Grace Hopper Celebration (GHC) in Anaheim, a conference for women in computing, has been canceled just two weeks before its start. Brenda Darden Wilkerson, president and CEO of AnitaB.org, the nonprofit that manages the convention, said in a press release that "both individual registrations and sponsorship commitments came in significantly below our expectations," leaving GHC short of the money needed to cover its operating costs. The circumstances behind the cancellation have also hurt AnitaB.org’s finances, and it is now considering strategic alternatives and looking at what programming it can offer in the future.

With the event called off, attendees were told to cancel their own travel and lodging arrangements (which are on the attendee). Fees already paid have not been addressed, and depend on the nonprofit getting a clearer picture of its finances. Sponsors and exhibitors are being handled directly through contacts, but no information on refunds was available at the time of posting. Meanwhile, AnitaB.org is asking employers with scheduled career-fair interviews to keep those conversations going directly “where possible” — but without any guarantees.

The event, set for Oct. 27 – 30 at the Anaheim Convention Center, had announced speakers — including journalist Kara Swisher, Cloudflare co-founder Michelle Zatlyn, and futurist Sinead Bovell — with Cathy Hackl hosting, and GHC co-founder Telle Whitney expected to give a talk.

"I’m in shock. The notice just came in," Hackl told Forbes. Writer and TheLi.st co-founder Rachel Sklar called the conference "a mainstay" on X.

The conference carries the name of Grace Hopper, the Navy rear admiral the service calls a pioneer in computer science. AnitaB.org says 700+ organizations take part each year. The event intended to cover AI fluency with a career fair for hiring — just as tech firms are cutting jobs and ascribing many of the cuts to AI. Its sponsors reportedly include Capital One, CVS Health, Disney, Goldman Sachs, Google, Intuit, and Morgan Stanley.

Looking at its financial history, AnitaB.org lost $14.6 million in 2024 on revenue of $27.5 million and expenses of $42.1 million, according to its annual IRS filings. Its net assets roughly halved while liabilities nearly doubled. “Contributions and grants” fell from $11.2 million in 2023 to just $724,350 in 2024. Attendance also was in decline — from 29,000 in 2023 to 17,000 in 2024 — counting in-person and virtual attendees. The 2024 filing put GHC’s own expenses at $26.9 million against $22.4 million in revenue. The conference's 2024 gap suggests a pattern that may have worsened.

It’s unclear what this means for GHC moving forward — 32 years after Anita Borg and Whitney founded it in 1994. AnitaB.org says it will contact registrants about their fees by Oct. 26, and further announcements are expected in the coming weeks.

SK hynix has detailed plans to reduce reliance on power-hungry CPU cores with an in-house core named a Hynix Transaction Processing Unit (H-TPU). Not to be confused with an AI accelerator, an H-TPU would assist with repetitive work handled by an SSD, which usually demands more cores on a controller as drives get faster. These new cores are placed in clusters and would handle routine I/O with a four-stage, in-order pipeline, while management is left to the traditional Arm CPU. The new, tiny cores are claimed to draw only about 2.5% of a general-purpose CPU core’s power, with just around 4% of its area. Now, the company plans to apply H-TPU across its portfolio of products, TheElec reports.

The company’s VP of system-on-chip (SoC) design, Koo In-jae, spoke at ISOCC 2026, the International SoC Design Conference, earlier this week, saying that SSD controller CPUs are at their limit on power and area. In the talk, titled “From SSD Controllers to AI Memory SoCs,” he said that PCIe bandwidth doubles every generation, and controller CPU clocks and control capability reportedly can’t keep up. SK hynix reportedly plans to apply H-TPU across its NAND products, including next-gen enterprise SSD controllers. That’s where the unending chase for IOPS makes the problem most evident.

Koo’s comments underline the issue of scaling, which is evident in the “more cores” solutions found in competitor products. Marvell’s PCIe 6.0 Bravera SC6 uses 12 Cortex-R82 cores in two six-core clusters with three Cortex-M7 cores and a secure Cortex-M3. Compare this to its PCIe 5.0 predecessor, the Bravera SC5, which lists 10 Cortex-R8 and Cortex-M7 cores plus a Cortex-M3 for security. Core counts have climbed with PCIe speeds out of necessity.

SK hynix’s answer is a core of its own design: the H-TPU, kept small and programmable. It comes with a dedicated compiler and other development tools for specialized code. It’s stated to use a four-stage pipeline with in-order, or sequential, execution. It is not superscalar, does not use out-of-order units, and should not be confused with a tensor processor for AI. It is designed to handle read and write command processing, manage metadata, and handle buffer control, all repetitive tasks.

Storage control requires more than 100 detailed functions, which is not ideal for a monolithic CPU. Instead, SK hynix broke those functions up and spread them across “dozens of small TPU clusters,” according to ZDNet Korea (translated). Each H-TPU therefore has a specialized job. The total number of H-TPUs is more than 100; the function count above is a separate figure. However we currently have no details on how many cores each cluster holds.

The main CPU still handles error recovery and exception handling, plus storage-policy management, so the H-TPU complements the CPU: offloading, not replacement. The design idles the cores a given I/O doesn’t need, which reportedly drop into a minimum-power mode. Neither report names the CPU core behind SK hynix’s 2.5% power and 4% area figures.

Splitting the workload this way is not a new idea. Phison’s CoXProcessor, which pairs Cortex-R5 cores with hardened macros to offload repetitive firmware at wire speed, has been in products for some time. The company’s E18 SSD controller uses two lower-clocked Cortex-R5 cores to supplement the three main ones. On the enterprise side, Phison’s X1 used two Cortex-R5 cores plus up to 32 “micro cores,” each dedicated to one or two tasks. H-TPU takes this approach to a larger scale.

While the talk itself is light on detail, we discovered multiple SK hynix patents that describe a similar split between small cores and a CPU. U.S. patent 11,675,537, first filed in Korea in November 2020, details a CPU-run control plane and an I/O plane of many small processors, sorted into four groups by job. A command passes through all four in order: host for ingestion, cache, map, and NVM to the NAND. The processors “configure a pipeline for the data I/O operation” this way, letting the CPU handle any exceptions. That pipeline runs across many cores and is unrelated to the four-stage pipeline inside each H-TPU.

In the patent’s example, each small core is around “200,000 logic gates” rather than the “seven million logic gates” of the CPU, or about 2.9% of the CPU’s gate count. These are not fixed elements, as “firmware may be driven in each of the TPUs,” making them more adaptable than the hardware circuits the patent calls “difficult to modify.” The patent spells out TPU as “Tensor Processing Units,” but, again, this should not be confused with AI accelerators. H-TPU shares that programmable approach, but the next step SK hynix described moves some routine jobs into fixed hardware.

This next step is hardware automation (HWA), with command processing, address lookup, and buffer copies moved to dedicated circuits. The CPU and H-TPUs still handle exceptions and key policy decisions. Moving to this framework is meant to keep completion times predictable, which is necessary with I/O, especially for today’s high-IOPS enterprise SSDs.

SK hynix has filed on fixed-hardware paths before, with a 2014 filing by its San Jose-based unit and, later, with U.S. patent 12,216,914, first filed in Korea in 2022. The latter describes a “write automation circuit” and says “a task without intelligent control can be handled or processed through the hardware layer,” while firmware keeps jobs such as garbage collection. The former went further, sending basic I/O commands down a path “completely implemented in hardware,” with anything it couldn’t handle being sent upstream.

The H-TPU itself is reportedly being used in “Storage Next,” Nvidia’s name for the joint AIN P project with SK hynix. Storage Next targets 512-byte or more limited access with NAND, which traditionally aims at higher operating sizes. SK hynix also plans to apply it to high-bandwidth flash (HBF), which the outlet said is due next year. HBF stacks NAND dies for AI inference, targeting high-bandwidth memory (HBM) levels of bandwidth but with far more capacity, with up to 512GB per stack versus 64GB for HBM4.

For HBF, AI inference reads outnumber writes around 300,000 to 1, with the AI compiler and runtime passing pre-analyzed dataflow to the HBF SoC. Proper buffer management and prefetching based on that dataflow are meant to hide the slow NAND latency behind compute. Size is important in HBF stacks, so a traditional multi-core Arm design is likely less practical.

H-TPU has yet to be proven in an actual enterprise SSD controller product, and no date has been given. The move from general-purpose CPU cores to specialized single-job cores and circuits matches the type of workload SSDs handle, and the demands on storage are only increasing as AI servers become memory-constrained.

SK hynix’s statements and patents support an evolution to H-TPU and beyond to HWA, with H-TPU itself headed for traditional NAND and next year’s HBF. SSD controller manufacturers must be willing to adapt, as simple scaling is suboptimal even at current PCIe levels, let alone the speeds promised for PCIe 7.0 and 8.0, the latter headed for final ratification in 2028.