As advanced packaging technologies like EMIB and CoWoS become yet another battlefield in the semiconductor industry, outsourced semiconductor assembly and test (OSAT) companies are trying new tools in a bid to offer services that others do not. This week, LG Electronics Production Technology Institute (PRI) signed a contract with an OSAT to supply it with a maskless laser direct imaging (LDI) lithography tool that can be used to build metal-interconnect patterns in semiconductor packaging, potentially with higher yields than currently available tools, reports ETNews.

LG-PRI's Laser Direct Imaging (LDI) system is a maskless lithography machine designed to pattern fine metal interconnects for advanced semiconductor packaging. While the company has developed various versions of the machine, its highest-resolution version can produce 1.5-µm line-and-space (L/S) patterns, which should be fine to 'print' wiring pitches of about 3 µm. The production equipment uses a 405-nm laser-diode light source and can process substrates as large as 600 × 600 mm, according to various media reports.

LG positions its LDI system primarily for advanced semiconductor packaging using organic and then glass substrates, displays, and MEMS. Yet, it can also be used to build high-density printed circuit boards (PCBs) for mobile devices or prototype purposes.

LG is entering an already established direct-imaging market led by KLA, Screen Holdings, Limata, and ORC, but participated in by a dozen manufacturers from Germany, France, Switzerland, Japan, and even China. What is notable is that LG is offering LDI systems with line/space capability down to 1.5-µm, which means it is targeting the higher end of the market. Yet, to establish a position, LG plans to price its LDI system competitively.

Another way to pattern substrates

There are many ways to pattern substrates, including photolithography, e-beam lithography, nanoimprint lithography, and laser direct imaging, just to name a few. LDI is a maskless lithography process in which a laser exposes a digitally generated circuit pattern directly onto a photoresist-coated substrate, rather than transferring the pattern through a physical photomask. Instead of a photomask, an LDI system uses a digitally controlled pattern generator and projection optics, which resembles how a laser cinema projector projects a digital image onto a screen, except that LDI projects a circuit pattern onto photoresist. After development, the exposed resist leaves a pattern that defines where metal interconnects will be formed in later processing steps.

LG's LDI machine can produce down to 1.5-µm line-and-space patterns, which is good enough for chip substrates and even redistribution layers (TSMC CoWoS-R/-L uses RDL interposers with a minimum 4-µm pitch, or 2-µm line width/spacing). In contrast, competing products offer 1-µm, 3-µm, and 5-µm versions for different applications. While LDI in general cannot boast the resolutions offered by modern DUV, EUV, or e-beam lithography machines, LDI trades ultimate resolution for vastly higher throughput and large-area processing, exactly what the doctor ordered for production of PCBs or chip packaging. With current-generation LDI, the RDL interposer is the most advanced thing that these devices can pattern, as both CoWoS-S and CoWoS-L/EMIB-like technologies require considerably higher resolution. Meanwhile, there is another advantage that LDI machines have over lithography systems that rely on photomasks.

Because the image is generated digitally, the system can create and calibrate patterns in real time, while projection optics, precision alignment, and stage control position the pattern accurately on the substrate. This capability is important because the dimensions/geometry of packaging substrates can vary and because organic substrates can expand, contract, or warp during processing. Given that we are talking about a 1.5-µm-scale wiring pattern, any shift from the nominal layout may result in a solder bridge or a faulty contact, which means yield loss. That said, the ability to adjust the pattern to the peculiarities of a substrate may be a game-changer for OSATs, their customers, and a major selling point for devices that can do it.

A new kid on the block? Not really

Unlike competing chaebols Samsung and SK Group, LG Group does not produce chips, even though its divisions supply various materials and components for the semiconductor industry. To that end, it is perfectly reasonable for the company to enter the market for tools for the production of chip packages or PCBs.

In fact, LG PRI is not entering the exposure-equipment business from scratch. PRI traces its history to the Goldstar Production Technology Research Institute, established in 1987, and has worked on manufacturing and productivity technologies covering semiconductors, displays, and rechargeable batteries. Specifically, LG had already commercialized LDI technology for display manufacturing and supplied such equipment to LG Display.

As a result, the semiconductor packaging-grade equipment represents an expansion of an existing LG technology into a new market rather than the development of an entirely new exposure platform from scratch and without any experience. Interestingly, LDI is the first element of LG's semiconductor equipment ambitions. The company reportedly plans to expand its portfolio into high-bandwidth memory (HBM) inspection equipment as well as through-glass-via (TGV) laser systems for glass substrates.

Prospects

Before LG expands to inspection or laser drilling tools, it will have to establish itself as a producer of reliable tools used for chip packaging, which will likely take years. For now, the significance of the deal with the undisclosed OSAT is less about business and more about the fact that an OSAT decided to give LG's LDI machine a try. Moving from university R&D installations to an OSAT mass-production facility provides LG a starting point for pursuing additional external orders.

Whether LG can establish itself alongside Applied Materials, ORC, or Screen will depend on how its equipment performs in production and whether its emphasis on competitive pricing proves sufficient to persuade more packaging companies to adopt the system.

In any case, a new Wafer Fab Equipment player is here, which is good news considering shortages of virtually all chipmaking tools. While LG's entrance will hardly have any noticeable impact on the market for at least a couple of years, another supplier could eventually add much-needed capacity, increase competition, and give chipmakers and OSATs another source of advanced packaging equipment.

Nvidia has rejected a report claiming that it plans to begin small-batch shipments of a language processing unit tailored for Chinese customers by the end of 2026, with several Chinese orders already placed. "The reporting in The Information on NVIDIA's LPU is incorrect. We have no LPU sales in the China market today, and no China-specific LPU product in our roadmap," an Nvidia spokesperson told Tom's Hardware on Thursday. The Information's story, which cited two Nvidia employees, said the chip is a variant of the Groq 3 LPU Nvidia announced at GTC in March, and that its silicon is unchanged because it already falls within U.S. export rules.

The LPU was designed as a decode co-processor for the Vera Rubin platform, and Vera Rubin can't be sold in China. The Information's sources said Nvidia rewrote the software that splits work between the GPU and the LPU so the accelerator can run alongside processors that are available in the country.

The publication said Nvidia didn't respond to requests for comment over several days before publishing, and that it's unclear whether Beijing would allow the orders to proceed. Chinese officials blocked purchases of the H20 last year and only recently told companies they'd permit some H200 imports, so U.S. compliance alone doesn't guarantee the chips can be delivered.

Back in March, it was reported that Nvidia was preparing LPUs for China, with Jensen Huang saying two days later that the story was "totally false.” Thursday's statement is narrower than Huang's, addressing current sales and a China-specific product. Nvidia hasn’t clarified whether the standard LPU will ship to Chinese buyers. Huang told CNBC in May that Nvidia had "largely conceded" China's AI chip market to Huawei.

The Groq 3 LPU is built on Samsung's 4nm process with 512MB of SRAM per die and no HBM, and Nvidia said at GTC that it would ship in Q3 2026 to customers including OpenAI. U.S. export thresholds for China are set on compute density and bandwidth, and an SRAM-only decode accelerator with no HBM stack is the kind of part that can still be exported under them without a cut-down SKU, which is the mechanism The Information's sources described.

Huawei's Ascend 950DT, which the outlet named as the LPU's direct competitor, is optimized for decode and training and is due in Q4 2026, with the prefill-focused 950PR already in production since April. ByteDance and Tencent each took delivery of roughly 10,000 H200s in recent weeks, according to a Financial Times report this week, the first meaningful Nvidia accelerator volume to enter mainland China since December's U.S. approval.

Synopsys has published silicon results for what it calls the first 3D PCIe 6.0 test chip, a 5nm PHY built into a face-to-face stacked package that runs 64 GT/s per lane and up to 128 GB/s across an eight-lane link using PAM4 signaling, with receiver eyes clearing the standard's bit error rate requirement. The company says it got there by pulling apart an existing 2D PCIe 6.0 test chip, adding through-silicon vias, and redoing circuit design and signoff against 3D process design kits, according to its blog post.

In monolithic chips, PCIe PHYs sit at the perimeter of the die, right next to the package I/O connections, helping keep traces to the substrate short so attenuation and reflections remain manageable. A 2.5D package preserves that layout by parking the PHYs along the outer edge of the outermost chiplets. Face-to-face hybrid bonding removes the option. The bottom die is flipped so its redistribution layer meets the redistribution layer of the logic die above it, which leaves the PCIe PHYs facing away from the substrate they need to reach. Instead, the signals travel down through vias cut into the silicon.

Every TSV passes through active silicon and needs a buffer around it, so the vias can't be dropped wherever the PHY happens to sit. "You rarely drill straight down into the package substrate," Manmeet Walia, executive director of product management at Synopsys, said to Electronic Design, which reported that routing has to climb to one of the upper metal layers and reverse direction before descending.

Walia told the publication that electromigration and layout rules change substantially in 3D, that via count is a tradeoff between bandwidth and signals corrupting each other, and that customer logic sitting over the PHY's path down to the substrate is a challenge that Synopsys expects to work through iteratively, design by design. PAM4 leaves less room for that kind of error than the NRZ signaling used through PCIe 5.0, since it packs two bits into each symbol.

Fujitsu's Monaka processor takes the opposite approach, instead stacking four N2 compute chiplets carrying 144 Armv9 cores face-to-face on N5 SRAM chiplets using hybrid copper bonding, then putting the memory controllers and the PHYs for its 12 DDR5 channels on a separate and comparatively large I/O die rather than inside the bonded stack.

PCIe generations arrived roughly five to seven years apart for most of the standard's life and now release about every two years, with the Gen 8 specification due in 2028 at 256 GT/s per lane. Walia told Electronic Design that a further shift is coming with 3.5D packaging, where the PCIe PHYs get stripped out of the bottom die entirely, replaced with UCIe, and relocated to a side chiplet on the interposer that acts as a multi-protocol hub for Ethernet, PCIe, and CXL. Synopsys hasn't put a date on that. Its blog says leading-edge customers are evaluating angstrom-class process technologies for the top dies in their stacks.

SMIC posted its first $3 billion quarter earlier this month, with revenue up 36.1% year on year, net profit nearly tripling to $479.2 million. Co-CEO Zhao Haijun told analysts the next day that the Shanghai foundry will charge more for wafers processed in the third quarter after price negotiations concluded in the first. Utilization hit 93.7% against demand Zhao said SMIC can't fully meet, driven by Chinese AI data center buildouts that U.S. export controls have cut off from TSMC and Samsung at the leading edge. "Since there's still a big gap between industry-leading wafer prices and SMIC's current prices, we need to negotiate with customers for fairer pricing," Zhao said on the call.

The quarter blew SMIC's own out of the water on every front. The company had guided to 14% to 16% sequential revenue growth and a 20% to 22% gross margin; it delivered 20% growth to $3.01 billion and a 25.3% margin, up from 20.1% in Q1. Wafer shipments rose 14% quarter-on-quarter to 2.9 million 8-inch equivalents, blended selling prices climbed 5.7%, and Q3 guidance calls for a 26% to 28% gross margin. China accounted for 90% of revenue.

Demand isn’t coming from GPUs, however, with Zhao commenting that the surge came mostly from AI chips other than CPUs and GPUs, such as logic ICs, BCD power-management parts, and optical transceiver components, all in short supply. Meanwhile, growth in SMIC’s AI peripheral segment is expected to be around 40% for the quarter, while industrial and automotive chips rose to 16.5% of wafer revenue from 10.6% a year earlier.

From bust to boom

SMIC's utilization sat at 68.1% in the first quarter of 2023 and averaged 75% that year as net profit fell more than 60% and gross margin dropped 16.4 points to 21.9%. As late as early 2025, it was reported that SMIC and Hua Hong were cutting mature-node prices to defend share against a wall of new Chinese capacity. The company that spent 2023 and 2024 discounting into overcapacity spent 2026 raising prices by around 10% in December, negotiating targeted increases in capacity-constrained segments in February, and applying another round to Q3 wafers.

Export controls did most of the work, with Washington’s restrictions keeping China's AI accelerator demand away from TSMC. Beijing has been redirecting that demand inward: the government wants 70% of silicon wafers sourced domestically this year, and a Bloomberg Intelligence survey of 60 Chinese tech executives in June found firms plan to spend 46% of their AI accelerator budgets on local chips over the next 12 months, up from 30% now. SMIC is the only Chinese foundry that mass-produces 7nm-class logic, which makes it the sole domestic route to silicon for Huawei's Ascend line and Cambricon's accelerators. A protected buyer pool, along with a mandated shift to domestic supply and a single qualified supplier at the leading edge, produces a textbook seller's market.

Hua Hong, China's second-largest foundry, reported utilization of 102.8% in the same week, with record revenue of $717.5 million, up 26.8% year on year. TrendForce data shows foundry prices across China rose 5% to 15% between Q1 and Q2, with a third round of increases being prepared for the second half. TSMC is reportedly raising prices across all its advanced nodes too, so SMIC's hikes track a global trend, but SMIC is doing it from a captive position TSMC doesn't have: its customers have no other choice.

China's AI chip designers post record first halves

Cambricon's first-half revenue rose 108% to 6 billion yuan (c. $890 million) with net profit up 122.6% to 2.3 billion yuan, per its Shanghai Stock Exchange filing reported by the South China Morning Post. Moore Threads grew first-half revenue 147% to 1.74 billion yuan and cut its net loss by 96%, and Biren projected first-half revenue growth of more than 1,850% off a small base ahead of a Hong Kong IPO. Memory maker CXMT raised $8.6 billion in Shanghai's biggest-ever semiconductor listing last month and surged 466% on debut to become the most valuable company on any mainland exchange. Every one of these firms sits on the U.S. Entity List or depends on suppliers that do, and every one just posted record or near-record numbers.

Beijing had until recently been blocking Chinese imports of U.S. accelerators. The US approved around 10 Chinese firms to buy Nvidia's H200 in May, but China had been blocking the purchases to protect domestic suppliers. Under Secretary of Commerce Jeffrey Kessler told a congressional hearing on July 14 that "very few" H200s had actually shipped. Officials have relented as of August 19, with ByteDance and Tencent each having received around 10,000 H200 chips, the first meaningful deliveries since the U.S. approved around 10 Chinese firms as buyers.

Some 20,000 delivered accelerators against Huawei's target of 600,000 Ascend 910Cs this year leaves Chinese cloud spending, which Goldman Sachs pegs at roughly $102 billion for 2026 in combined AI capex across Alibaba, Tencent, ByteDance, and Baidu, landing overwhelmingly on domestic silicon.

SMIC's 7nm yields and the HBM shortage

SMIC's leading-edge economics remain brutal, however, with industry sources cited by the Financial Times putting SMIC's 5nm and 7nm prices 40% to 50% above TSMC's with yields of less than a third, a consequence of running multi-patterned DUV on nodes designed for EUV. The wafers SMIC is repricing are overwhelmingly mature-node parts, where its cost position is sound; the advanced capacity that feeds Ascend production stays yield-limited and expensive per good die regardless.

Memory, not logic, caps accelerator output anyway, and SemiAnalysis estimates Huawei has been drawing down a stockpile of roughly 13 million Samsung HBM stacks acquired before the late-2024 controls, and domestic HBM from CXMT will cover only a fraction of 2026 Ascend targets.

SMIC's own profit surge also comes with a glaring asterisk: CFO Wu Junfeng said the near-tripling was boosted by a one-time gain from a subsidiary. Demand for its silicon rests largely on policy rather than proven end markets, with an analyst tally cited by Asia Times putting China's top 11 listed chip firms at a combined average of roughly 122 times projected 2026 earnings.

Japanese chemical maker Ajinomoto has reportedly told customers in mainland China that it will cut supply of ABF, the insulating build-up film that's used in nearly every high-end processor package, by 30%, according to a report from the Chinese outlet JW Insights, which cites unnamed supply chain sources.

If true, that would be painful for Chinese customers like Shennan Circuits, Xingsen Technology, and Shenghong Electronics, who rely on Ajinomoto's reported 95% global market share of the film. In contrast, China's self-sufficiency rate is thought to sit below 5%.

JW Insights attributes the cut to Ajinomoto prioritizing Japanese customers and core overseas accounts, which supply the FC-BGA substrates under Nvidia, AMD, and Intel accelerators, over mainland buyers. Whether or not the 30% figure holds up, the squeeze is well documented, and China's response was underway long ago.

A confirmed shortage

Ajinomoto's ABF production ran at roughly 2 million square meters per month at full utilization in the second quarter. The company has committed ¥25 billion (around $156 million USD) since 2023 to expand capacity by about 50% by 2030, and land purchased in Kani City, Gifu Prefecture, hosts a third plant not expected to come online until around 2032.

In the fiscal year ended March 31, Ajinomoto reported that ABF sales grew 25% with margins above 50%, and the share of its film going into servers and networking silicon reached 70%, up from 40% in fiscal 2017. According to Goldman Sachs, the gap between ABF substrate supply and demand will widen from around 10% in the second half of 2026 to 21% in 2027 and 42% in 2028.

Ajinomoto notified substrate makers in May of a roughly 30% price hike taking effect this quarter, two months after UK activist fund Palliser Capital disclosed a top-25 shareholding on March 31 and publicly demanded the company raise ABF prices by more than 30%. That hike is confirmed, even if the volume cut isn't. ABF material accounts for about 30% of a substrate's bill of materials, so the increase flows directly into the cost of every FC-BGA package built on it. We've been tracking ABF crunches since the shortage that constrained GPU production in 2021 and 2022, and the current cycle looks to be extending a pattern that's already hit BT resin substrates and T-glass cloth, where single Japanese suppliers also dominate.

China has three films in qualification

Huazheng New Material's CBF, developed with the Shenzhen Institute of Advanced Electronic Materials, is the most mature of China's three named alternatives. The film uses a modified epoxy resin with spherical silica filler, which routes around Ajinomoto's IP rather than copying it. According to reports coming from Chinese media, its mass-production yield sits at above 85%, with reliability testing reportedly having passed inside Huawei Ascend systems and validation underway at Xingsen and Shennan Circuits. Huazheng's first production line of 3 million square meters per year is said to be running at full utilization, and a second line doubling that is slated to come online at the end of 2026.

Lotus Holdings, best known in China as a producer of MSG, acquired 51% of Shenzhen Newface, the developer of NBF, in April for roughly ¥103 million. Newface is said to have qualified all products below nine build-up layers, with nine- to 11-layer films in development and validation underway at Taiwanese substrate makers. Ajinomoto itself is a food and seasonings company that derived ABF from its amino acid chemistry in the 1990s.

Hongchang Electronics' GBF, co-developed with Taiwan's Jinghua Technology, has been validated at a leading domestic OSAT and is in small-volume trial production, with scale-up targeted for the fourth quarter. All three films face the same challenge of downstream reliability qualification taking one to three years of thermal cycling, damp-heat aging, and electrical testing, often longer than the R&D itself, and the highest layer-count films under flagship AI accelerators remain unmatched domestically. Upstream inputs, including specialty resins and spherical silica filler, are themselves partly import-dependent.

Huawei's Ascend packaging sidesteps ABF

Huawei's Ascend 910C reportedly connects two compute dies on separate silicon interposers through an organic substrate, an approach SemiAnalysis has described as trading die-to-die bandwidth for yield and cost against Nvidia's CoWoS.

That architecture makes Huawei less dependent on the high layer-count ABF-based FC-BGA substrates that Nvidia's B200 and GB200, AMD's MI300X, and Intel's accelerators sit on, and Chinese reporting seems to position Ascend as the anchor qualification target for both CBF and GBF. Cambricon, Biren, Moore Threads, and Alibaba's T-Head, which package on conventional FC-BGA, are directly exposed to any mainland ABF supply disruptions.

China banned exports of dual-use items to Japanese military-linked end users back in January through Ministry of Commerce Announcement No. 1, following Prime Minister Sanae Takaichi's November remarks on a Taiwan contingency, with measurable fallout. Chinese exports of restricted rare earths to Japan fell roughly 51% year-over-year in the first half of 2026, Nikkei Asia reported, and Japan imported just 13 tons of dysprosium in the period, down 82% from two years earlier, per TrendForce.

Ajinomoto's move to cut ABF supply to China eight months later has obvious retaliatory optics, despite every account of the alleged cut attributing it to capacity allocation under AI demand. China's rare-earth controls have so far targeted materials where China holds the leverage, and ABF is a market where it holds none.

Meanwhile, BOE signed a three-year glass substrate agreement with Corning in May and designated glass-core packaging a strategic business in July, and Lens Technology announced a through-glass-via collaboration with Intel the same month, extending China's push into glass substrates as the longer-term route around Japanese film.

A glass core swaps out the middle layer of a substrate, but the chip package still needs insulating film built up on either side, so glass doesn't remove the need for ABF or its substitutes. None of China's glass projects has reached mass production either. Until that changes, China's answer to the reported cut depends on whether Shennan, Xingsen, and Shenghong qualify their domestic films.

Intel is set to raise $19.7 billion by selling new common stock in a bid to finance the building out of new production capacity, the development of next-generation leading-edge process technologies like 14A and others, and day-to-day operations. While the company does not assign money to a particular project, Intel needs to build capacity to land orders from large external clients, so capacity expansion will likely be a priority. According to Bloomberg, the share sale attracted $100 billion in demand.

Intel will sell 210,526,315 shares for $95 apiece through an underwritten public offering. In addition, participating banks have 30 days to acquire as many as 31,578,947 more shares at the same $95 price, minus applicable underwriting discounts. Should they exercise all their options, Intel could sell approximately 242.1 million shares altogether and increase the proceeds to roughly $23 billion. Without the additional shares, Intel expects net proceeds of approximately $19.7 billion after underwriting discounts, commissions, and estimated expenses. The transaction is scheduled to close on August 12, 2026.

Intel's market capitalization increased from roughly $90 billion last August to $491 billion at press time, so the time is right to sell some shares and raise some much-needed cash, as the company must compete against giants like TSMC and Samsung, which spend tens of billions of dollars every year on new fabs and advanced process technologies. Meanwhile, Intel's capitalization reached its all-time high of $673 billion on June 20, 2026.

Intel has not assigned the money it is going to raise to particular projects and says the capital can be used across the business, including for capital expenditures and working capital. The company is currently ramping up its Fab 52 in Arizona and is on track to start using adjacent Fab 62 when it needs to. In addition, the company still has to build its fab complex in Ohio, which is expected to cost over $100 billion when fully built, so it badly needs money.

In its risk disclosures, the company specifically mentioned Intel 14A — which is due to enter mass production in 2028 — and other advanced process technologies, manufacturing expansion required to support them, and the need to secure design wins and volume commitments from major external foundry customers. While Intel does caution that these long-term investments amounting to tens of billions may not generate adequate returns, it is impossible to land sizeable contracts from external customers without having production capacity readily available.

Interestingly, Intel also mentioned alternative financing arrangements, government grants, and the U.S. government's significant equity position in the company among relevant factors.

House Select Committee on China Chairman John Moolenaar has written a letter that demands the U.S. government enforce an existing export control measure designed to prevent Chinese companies from getting advanced chips produced by contract chipmakers like TSMC or Samsung Foundry.

When Joe Biden was about to leave the office in early 2025, he signed a law that required chipmakers to determine their end customers in a bid to prevent contract manufacturers from unknowingly fabricating chips using American technologies for companies that served as intermediaries for restricted organizations tied to the Communist Party or the People Liberation Army. The regulation was introduced after it was discovered that chips made by TSMC for China-based Sophgo were actually Huawei's Ascend 910B AI accelerators. However, the Trump administration announced in May 2025 that it would not enforce this semiconductor regulation known as the 'Foundry Due Diligence Rule,' which naturally created uncertainty about whether the foundry-focused requirements would be actively implemented at all.

"The announcement created ambiguity as to whether front-end fabricators like TSMC can export unpackaged advanced dies to non-approved designers located outside of China, without performing the due diligence specified in the Foundry Due Diligence Interim Final Rule (IFR)," the letter reads. "These exports enabled Huawei to obtain millions of controlled Ascend logic dies from TSMC, using its front company, Sophgo in 2023 and 2024."

Before the adoption of the 'Foundry Due Diligence Rule,' Chinese companies and/or their intermediaries could misrepresent chip specifications and end users when placing orders with TSMC or other foundries, which allowed restricted devices to be made despite U.S. export controls. Under the rule, foundries and OSAT providers exporting chips produced on 14/16nm-class process technologies or more advanced nodes must presume those devices qualify as controlled AI processors subject to a global licensing requirement, unless they meet an exemption. According to the letter, foundries have generally complied with these requirements since the rule took effect. As a result, Moolenaar essentially asks the government to enforce the existing controls rather than introduce stricter export controls.

Moolenaar believes that the Commerce Department's Bureau of Industry and Security could clarify its current stance on the Foundry Due Diligence Rule in two ways:

• By issuing guidance, which confirms that the worldwide Regional Stability (RS) licensing requirement still applies to exports from front-end foundries;
• By formally annulling the AI Diffusion IFR and amending §744.23 to explicitly restore that requirement for both foundries and OSAT providers.

Either approach would eliminate conflicting interpretations and reinforce enforcement of existing export controls, Moolenaar believes.

Apple used to be among a few companies willing to buy memory and other components worth billions of dollars under long-term supply contracts at fixed prices. But the artificial intelligence era represents a new reality with new purchasing champions, marking a tectonic shift in the high-tech world. Alphabet, Microsoft, Meta, and Amazon have purchase commitments totaling about $2 trillion, and a significant portion of these commitments are for memory, according to estimates by analyst Claus Aasholm. While the commitments are approximate, span many years, and should be generally taken with a grain of salt, they still reflect the direction the industry is moving.

Combined purchasing commitments from the four major hyperscalers shown in the chart —Amazon, Alphabet, Meta, and Microsoft — reached nearly $2 trillion by Q2 2026, with Alphabet and Microsoft accounting for the overwhelming majority of the total.

The rapid expansion suggests several major findings. Firstly, the AI infrastructure race is accelerating, not stabilizing. Secondly, AI infrastructure investments are driven by a handful of hyperscale cloud service providers (CSPs) whose long-term procurement commitments now vastly exceed those of traditional consumer electronics companies such as Apple.

Thirdly, memory has become a strategic asset — perhaps a competition weapon — rather than a commodity. Fourthly, suppliers of memory — both 3D NAND and DRAM — are gaining pricing power. Finally, demand for memory will likely drive major capacity expansion at Micron, Samsung, and SK hynix, even though so far these companies have been exceptionally disciplined about their capacity investments.

Almost $2 trillion commitments

Google shows by far the most aggressive increase in purchasing commitments, rising from roughly $140 – $150 billion in Q3 2025 to around $811 billion by Q2 2026 (though these are total purchase commitments by Alphabet, not specifically memory purchase commitments), while Microsoft follows a similar trajectory and reaches approximately $678 billion in total obligations, which includes, but is not limited to memory.

Meta is also ramping commitments substantially to around $349.3 billion (again, these are total commitments), whereas Amazon increased its commitments more gradually to roughly $130 billion. By contrast, Apple — which makes the world's most popular smartphone, and which was the largest consumer of memory just a couple of years ago — remains almost flat throughout the period at approximately $57 billion (of which $56.2 billion is payable within 12 months). Apple's commitments fall well short of Nvidia's commitments of $119 billion.

Again, we are talking about total purchase commitments, which include foundry capacity, 3D NAND, and DRAM memory, but are not limited to them. Alphabet, Amazon, Meta, and Microsoft all build custom silicon and custom servers, so a significant portion of these commitments is to various EMS providers.

While $1.968 trillion of purchase commitments for memory and storage alone would be an absurdly large amount of money, a huge portion of these commitments consists of contract manufacturing obligations as well as memory chips. This suggests that the foundry, 3D NAND, and DRAM markets are entering a new phase in which hyperscalers are willing to make vastly larger forward purchasing commitments than traditional consumer-electronics companies, giving suppliers a strong incentive to prioritize customers prepared to secure future capacity on that scale.

Strategic assets

While Claus Aasholm's chart is explicitly dedicated to memory, it does describe total purchase commitments of tech giants, so the chart can reasonably be read as evidence that memory and capacity at TSMC, Samsung Foundry, and GlobalFoundries are becoming a strategic asset rather than merely another component to procure at the best available price.

AI infrastructure requires enormous quantities of AI accelerators, DRAM (including HBM), and 3D NAND. Meanwhile, the supply of high-end memory (HBM) is constrained by fab capacity at major DRAM makers, whereas the supply of AI accelerators is constrained by both wafer capacity and foundries and packaging capacity at foundries and their OSAT partners. As a result, hyperscaler CSPs have an incentive to lock in supply years ahead, even if doing so requires exceptionally large purchasing commitments.

That also changes the relationship between semiconductor suppliers and their customers. In theory, a company willing to guarantee hundreds of billions of dollars of future purchases can effectively help underwrite expansions of foundry, memory, and advanced packaging capacity and, in return, secure priority access to scarce products and future process technologies. In reality, TSMC can well afford capacity expansion using the money it gets from hyperscalers and give priority to its largest customers. In this environment, access to DDR5, HBM, and 3D NAND memory becomes part of the competitive advantage rather than merely a procurement exercise.

This is also what makes Apple's position in the graph interesting: its purchasing commitments barely move while those of Alphabet, Amazon, Meta, and Microsoft surge. If the trend continues, Apple may remain one of the world's largest semiconductor buyers in absolute terms, but the question is whether it will be among the key customers that foundries, memory makers, and OSATs plan their future capacity expansions.

An inflection point

Perhaps the most interesting takeaway of the findings revealed by long-term purchase commitments is that the industry's center of gravity appears to have shifted.

During the smartphone era, foundries (well, TSMC has won) and memory suppliers often competed aggressively for Apple's business because of its enormous purchasing power. Today, hyperscalers building AI infrastructure are making purchasing commitments that dwarf those of traditional CE companies like Apple, which may well represent a strategic inflection point akin to the one Andy Grove described in his 'Only the Paranoid Survive' book.

Will this tectonic shift result in prioritization of customers capable of enabling future capacity expansions through massive long-term purchase agreements, or will foundries and memory makers remain more or less disciplined with their capacity expansions so as not to lose a lot when demand declines? This is a question that has yet to be asked.

In any case, the AI megatrend has transformed semiconductors — from foundries to advanced packaging and from DDR5 to HBM4 — into strategic assets that can no longer be treated as ordinary components procured on demand. And this is something that will continue in the long run.

Most megafactories usually take years to go from conceptualization to construction, but a recent drone flyover of the Terafab showed that progress has already started on the ground less than five months after Musk unveiled it. However, the video doesn’t do justice to the true scale of its footprint, so X user Nic Cruz Patane created a visualization to help us understand how large the chip manufacturing facility is.

The site will reportedly have a floor space of at least 100 million square feet, making it larger than Giga Texas (10 million sq. ft), the Pentagon (6.6 million sq. ft), Apple Park (2.82 million sq. ft), and the Mall of America (5.6 million sq. ft), combined. This also makes it significantly larger than New Century Global Center in Chengdu, China, with has an interior space of “just” 18.9 million sq. ft.

While this might seem like an absurd amount of space for chip manufacturing, it appears that the Terafab will need it because it’s going to be more than just a chip fab making AI processors — instead, it will be an all-in-one facility that will produce logic and memory chips, as well as have lithography, packaging, and testing under one roof.

Elon Musk started talking about building his own chip manufacturing facility in late 2025 and officially announced the project in March of this year. The reasoning behind this project is that both SpaceX and Tesla will require at least 1TW of compute, which is more than ten times that current global chip supply.

Nvidia CEO Jensen Huang warned that a project like this will be an “extremely hard” challenge, but it appears that Musk is willing to put his massive resources on the line for this. Intel CEO Lip-Bu Tan even said that he can “think of no better partner than Elon Musk” to explore “unconventional” ways of chip manufacturing.

Musk is no stranger to both leading and funding projects that otherwise seemed impossible. Although he did not found Tesla, his investment and leadership in the company led it to become an industry trailblazer in EVs. He fundamentally changed commercial space travel with SpaceX; something that used to be the purview of NASA and other national governments, and he also broke a record when he set up 100,000 Nvidia H200 GPUs in just 19 days back in 2024 — a process which Huang said usually takes four years.

It seems that Terafab is Musk’s biggest project to date, which is estimated to require up to $119 billion in investments. But even though it seems that this project already has a secure customer base in SpaceX and Tesla, the former acknowledges that there’s a risk that this ambitious megafactory may not be successful.

SpaceX and Tesla on Thursday formally unveiled plans for the initial phase of their Terafab project. The first stage of the plan — which is expected to use Intel's 14A process technology — is expected to require $16.8 billion in investment, while the completed campus is planned to encompass more than 100 million square feet of manufacturing space. The massive semiconductor manufacturing complex will be built in Grimes County, Texas, at a location that belongs to SpaceX.

According to SpaceX and Tesla, their combined demand for semiconductors is projected to exceed 1 terawatt (TW) of compute per year, which significantly exceeds today's global supply. In fact, SpaceX, Tesla, and xAI already consume a significant portion of contract chipmaking services available today, and can potentially justify building a dedicated fab that will exclusively serve Elon Musk's companies. In particular, Terafab is envisioned to exclusively produce AI inference processors for Tesla Optimus humanoid robots and Cybercab autonomous vehicles, as well as 'high-power' processors intended for SpaceX's space-based data centers. Meanwhile, SpaceX and Tesla have not disclosed when their combined demand for compute per year will hit the 1 TW benchmark.

Unlike a conventional semiconductor fab, Terafab is envisioned as a vertically integrated manufacturing campus where advanced logic devices, memory chips, packaging, and testing operations are housed together. Normally, logic and memory are produced at different fabs using different process technologies, whereas packaging and testing services are performed at different facilities. However, the companies believe that consolidating logic, memory, packaging, and testing in one location will not only shorten the production cycle but will also shorten time-to-yield by enabling faster iterative improvements.

Given the description and the goal of the project, this will be a massive facility. Yet, SpaceX and Tesla have said little about its capabilities; The only thing they have disclosed is that the current facility in Grimes County will feature '100 million square feet of manufacturing space.' The 100 million square feet (9.3 million square meters) figure immediately stands out because it is far beyond anything ever announced for a semiconductor manufacturing facility. For example, the total area of Samsung's Pyeongtaek campus is approximately 2.89 million square meters, or 31.1 million square feet. A single Samsung fab occupies about 120,000 square meters, or 1.29 million square feet. However, the key wording is important: '100 million square feet of manufacturing space' does not mean 100 million square feet of cleanroom space.

Based on an image published by SpaceX, the Terafab facility will occupy four massive buildings. It is unclear whether these buildings will be four phases of the project (i.e., logic, memory, and packaging will be made under one roof) or will serve different purposes (i.e., one building makes logic, another produces memory, yet another does testing and packaging). In any case, when fully built, Terafab will be a massive semiconductor production campus that will require significantly more than $16.8 billion.

The announcement claims that the Terafab facility will employ at least 3,000 people, and that between 60% and 80% of them will be Grimes and nearby Brazos County residents.

Terafab is expected to use water from Gibbons Creek Reservoir instead of local groundwater and feature on-site wastewater treatment as well as water recycling and conservation measures.

The announcement follows Tesla's groundbreaking earlier this year on a research semiconductor facility at the North Campus of Tesla's Giga Texas campus, which the companies describe as a precursor to Terafab.

China has started low-volume production of domestically developed immersion DUV lithography machines, with around five systems planned for this year and roughly 20 in 2027, according to a report from July 27, which wiped roughly $44 billion off ASML's market value.

The manufacturer was named as Shanghai Aishengna Electronic Technology Group by Reuters the following day, a state-owned company established in August 2023 with 7 billion yuan (around $1 billion) in registered capital that absorbed engineering teams from Huawei-affiliated startup Yuliangsheng and state scanner maker SMEE. The first units are due at SMIC, Hua Hong, and CXMT this year for production-line validation rather than volume output, but the machines are far from matching ASML's models and still require further testing.

Five machines represent about 3.8% of the roughly 130 immersion systems ASML deploys in a typical year (a class of lithography machines that put a super thin layer of liquid over the wafer during processing), with the European giant holding an estimated 98.7% of the total immersion market. The Chinese tool reportedly prints 28nm-class features in a single exposure and reaches 7nm, and theoretically 5nm, through multipatterning, the same route SMIC already runs on its installed ASML fleet. Neither company has confirmed the report, no machine has been shown publicly, and no throughput or overlay figures have been disclosed, against the 330 wafers per hour and 2.5nm overlay of ASML's current flagship immersion tools.

SMIC’s scanner

SMIC has been running a domestic immersion scanner, developed under the codename Mount Everest, since September last year, when the Financial Times reported that China's largest foundry had begun testing the Yuliangsheng tool with production-line integration targeted from 2027 after qualification.

FT compared the machine against ASML's Twinscan NXT:1950i, a system that entered the market in 2008, which puts the design roughly a decade and a half behind the tools ASML sells today. Yuliangsheng, founded in Shanghai in 2022 with 1 billion yuan (around $149 million) in registered capital, is understood to have delivered three lithography machines to fabs for testing by late last year, but this hasn’t been officially confirmed.

Many of the critical components needed for the machines are still imported from Japan, and delays at those local suppliers are what have capped 2026 output at around five units. The 2027 target of 20 machines is therefore an ambitious target that assumes a domestic component base that hasn't been established yet, and the imported parts remain within reach of any future export-control round.

18% litho localization

SMEE's most advanced shipping product remains the SSA600 series, a 90nm-class dry ArF scanner that was in mass production as of May last year. The 28nm-capable SSA/800 immersion tool the company announced in 2023 has never been deployed, and a state-media claim of its successful development was deleted shortly after publication. In December last year, SMEE won a roughly RMB 110 million ($16 million) single-source government contract for a KrF scanner specified at 110nm resolution and 15nm overlay, a useful indicator of where its production-grade capability is at the moment.

Domestic equipment took 35% of Chinese fab purchases in 2025, beating Beijing's 30% target and up from about 10% three years earlier, according to figures from China's semiconductor industry association. Etch and thin-film deposition passed 40% localization, and metrology reached 25%, while lithography managed just 18%, most of it in trailing-edge and packaging tools. From the end of 2025, new fab capacity additions are required to source at least half their equipment domestically, a mandate that guarantees the new scanners a customer base, whatever their specs turn out to be.

Etch, deposition, and everything else

Naura Technology became the world's fifth-largest chip equipment maker by 2025 sales, trailing only ASML, Applied Materials, Lam Research, and Tokyo Electron, and moving ahead of KLA. The company booked RMB 27.14 billion ($4 billion USD) in revenue in the first three quarters of 2025 against RMB 6.05 billion ($589 million USD) for all of 2020, holds an order backlog stretching into 2027, and has started developing lithography tools for the first time. AMEC grew revenue and net profit by more than 30% in 2025, while cleaning specialist ACM Research posted $901.3 million for fiscal 2025 and guided to as much as $1.18 billion for 2026.

SiCarrier, the Shenzhen firm widely linked to Huawei, debuted around 30 tools at SEMICON China in March 2025, spanning etch, deposition, metrology, and test, and was reportedly valued at RMB 65 billion ($9.63 billion USD) by September 2025 with more than RMB 10 billion ($1.48 billion USD) in orders. The U.S. added it to the Entity List in December 2024.

The sector's own leadership is less triumphant than the numbers suggest. In March, SMIC co-founder Wang Yangyuan and the heads of YMTC, Naura, and EDA firm Empyrean jointly described China's tool industry as "small, fragmented, and weak" and called for national consolidation, with Big Fund III's $47.5 billion being redirected toward lithography and EDA. The Aishengna venture, which merged the Yuliangsheng and SMEE teams into one state-owned vehicle, looks like the first product of that pressure to consolidate. China spent a record $49.5 billion on wafer fab equipment in 2024, per SEMI, and remains the world's largest buyer through 2027, even after a pullback in 2025.

EUV lithography

A Reuters investigation in December 2025, dubbed China’s “Manhattan Project,” described an operational prototype EUV light-source machine in a high-security Shenzhen lab, completed in early 2025, that generates EUV photons but hasn't yet exposed a wafer. More than 3,000 researchers are said to work across the program, with Huawei playing the coordinating role and SMEE handling system integration.

Two teams are chasing the light source: one led by Lin Nan, a Beihang University professor who worked at ASML from 2015 to 2021, has a solid-state laser-produced-plasma design running at 3.42% conversion efficiency against the roughly 5.5% commercial viability required, while Zhao Yongpeng's laser-assisted discharge plasma group at Harbin Institute of Technology has reached around 100W of EUV output against the roughly 600W that ASML's production sources deliver.

Beijing's target is chip output from the machine by 2028, with Reuters' sources calling 2030 more realistic. A separate strand of reporting described a reverse-engineered prototype built around an intercepted Cymer light source that has likewise produced nothing. Earlier claims of a Huawei EUV trial production in 2025 and mass production in 2026, which circulated via Chinese media in March 2025, were never confirmed by any primary source. Tsinghua University's accelerator-based SSMB concept, which would need a synchrotron of a staggering 100 to 150 meters in circumference, remains an academic project.

Export controls

The MATCH Act, introduced in the House and Senate in early April, would ban not only sales of immersion DUV tools to SMIC, Huawei, Hua Hong, CXMT, and YMTC but also the servicing of machines already installed, and would give the Netherlands and Japan 150 days to align.

At this stage, it remains a bill, not a law, but servicing restrictions would strike directly at the installed ASML base that produces every advanced chip China currently makes, including SMIC's N+3 node in Huawei's Kirin 9030. Chinese fabs have been preparing for exactly that scenario by using third-party engineers and gray-market parts to Frankenstein older ASML machines.

ASML's China exposure is already shrinking on schedule, with the country representing 20% of system sales compared to 41% in 2024 and 33% last year, even as the company raised full-year guidance to €43 to €45 billion in July. Likewise, Applied Materials expects to lose $600 to $710 million in China revenue this fiscal year.

Ultimately, three markers will indicate whether China’s domestic DUV program is a legitimate rival or yet more state-sanctioned hot air. The main one would be validated production wafers from an Aishengna tool at SMIC, Hua Hong, or CXMT with published throughput and yield, followed by delivery of anything close to the 20 machines planned for 2027, and a first exposed wafer from the Shenzhen EUV prototype before the 2028 target set by Beijing.

China has revised its regulations concerning protection of integrated circuit (IC) layout designs developed domestically. The new regulations are intended to make it harder for Chinese companies to obtain legal protection for copied chip designs by tightening originality requirements, registration procedures, and infringement remedies, Reuters reports. As a result, it will get harder for underperforming China-based companies to copy ICs developed by their more successful rivals. Meanwhile, Chinese chipmakers will be allowed to produce their designs in Taiwan or South Korea.

The amended regulations apply to physical chip layout designs that define how circuit elements are arranged on silicon and represent a substantial amount of engineering work, including for companies that specialize in chip design rather than manufacturing. To qualify for legal protection of their IC layouts, applications must now demonstrate that the layout was independently developed, formally attest that the design is original, and specify which parts of the layout constitute their own creative contribution (perhaps to give authorities an idea about which were licensed or obtained from open sources). As a result, authorities will be able to filter out weak claims and distinguish companies with strong technological capabilities. Furthermore, they will also be able to determine whether a particular chip was designed and built in China, or its alleged developer obtained its product elsewhere and attempts to disguise it as a 'Made in China' silicon.

The new rules also strengthen enforcement. From mid-October and onwards, in infringement disputes, courts may determine compensation based either on losses suffered by the rights holder or profits earned by the infringing party. Punitive damages will also become an option. In addition, the regulations clarify procedures for licensing, transferring, or using IC layout-design rights as collateral. Organizations that develop protected layouts are also required to provide reasonable rewards and payments to personnel responsible for creating those designs.

Chinese policymakers were also reportedly considering measures to prevent strategically important domestic technologies from being transferred abroad, acquired by foreign companies, or produced overseas. If these strict proposals were approved by the CCP and the government, Chinese chip designers would be unable to produce their chips at TSMC in Taiwan or Samsung Foundry in South Korea, and would force them to exclusively make them domestically at Semiconductor Manufacturing International Corp., Hua Hong, and other domestic contract producers that are decades behind market leaders.

The report claims the updated regulations reflect the strategic importance China now assigns to technologies developed by its domestic semiconductor industry. For now, it is evident that China is not ready to implement overseas production of advanced designs. However, the report does not explicitly claim they are completely off the table, according to Reuters.

The updated rules were signed by Premier Li Qiang on July 23 and will take effect on October 15.

Drone flyovers of Elon Musk’s new Advanced Technology Chip Fab (ATCF) in Texas have been shared on social media. The videos and photos come courtesy of flight instructor and drone videographer Joe Tegtmeyer (@JoeTegtmeyer), who regularly documents the progress of Giga Texas and Starbase projects. Considering that the fab was only announced on March 21 this year, groundwork has been brisk, and in a follow-up post, Tegtmeyer states progress has “hit another gear.”

In the above post, the all-things-space enthusiast notes that the ATCF already appears to be very well defined. “GeoPiers are at work on the part of the foundation that has had gravel mix placed on the top soil and more work grading on the south end,” he explains.

A few days later, there was an update with progress clearly accelerating, according to Tegtmeyer. As well as commenting on the shape of the facility becoming ever clearer and construction materials continuing to be stockpiled, there are other important signs of progress. Specifically, “4 new permits were filed in the past few days for the large trailer complex that houses the general contractors and the temporary Tesla offices for the new facility,” noted the enthusiast. “[It is] a great sign that things are progressing rapidly behind the scenes to fit out the facility when construction progresses far enough to allow for equipment installation.”

Importantly, Tegtmeyer reminds his followers that the ATCF is not the Terafab that will be built ~ 100 miles or so to the East in Grimes County, Texas. Rather, the ATCF is the equally vital but “smaller development facility that is the first part of the overall AI Chip development program.”

The ATCF is a joint Tesla–SpaceX facility, and is a keystone for the Tesla, SpaceX, and xAI accelerator chips to come. It is expected that chips from the ATCF will combine logic, memory, and advanced packaging under one roof. Projects spawned from here are destined to support Tesla cars and Robotaxis, Optimus robots, and upcoming Earth-orbiting AI data centers.

That’s distinct from the much larger, multi-phase, vertically integrated, 1TW/year Terafab megaproject, which will see collabs between Tesla, SpaceX, xAI, and Intel. It has massive AI computer production ambitions to feed terrestrial and space-based AI systems. We are still awaiting evidence that the Terafab has moved beyond the pre-construction phase.

If there were any doubt about the seriousness of Musk's semiconductor design and fabrication ambitions in these and other progress reports, ASML CEO Christophe Fouquet recently confirmed talks with Musk had taken place about building one of the largest chip manufacturing operations ever attempted. SpaceX has also already filed for a $55 billion facility in Grimes County, Texas, with potential expansion costs reaching $119 billion, and phase one potentially beginning before the end of the year. Meanwhile, it is good to see the rapid progress of the smaller ATCF.